In this paper we present an overview of several techniques that are used when the layout pitch and feature size become significantly smaller than the minimum resolution of the lithographic process. We consider several multi-patterning (MP) techniques, in which a single layer is decomposed into two or more masks and printed in multiple stages. We also introduce the direct self-assembly (DSA) technology, where features several times smaller than the minimum lithographic resolution form spontaneously due to self-assembling, or self-organizing, formation of block copolymers.

Multiple patterning lithography is the most likely manufacturing process for sub-32 nm technology nodes. Among different multiple patterning methods, self-aligned patterning has attracted much interest due to its robustness against overlay errors. However, self-aligned patterning compliance is subject to the litho-friendliness of the applied decomposition method. This brief establishes self-aligned triple patterning (SATP) decomposition requirements and proposes a litho-friendly layout decomposition method. First, the major SATP litho-friendliness requirements are explained. In-silico experiments on SATP process indicate that layout features printed by the structural spacers are the most accurate ones. Therefore, we propose an ILP-based decomposition which avoids decomposition conflicts and maximizes the use of structural spacers simultaneously. Experiments reveal that the proposed method improves overlay robustness and line-edge roughness of the attempted test cases.

This paper establishes self-aligned double patterning (SADP) decomposition requirements and proposes a litho-friendly layout decomposition method. First, we explain the SADP-specific printability requirements that should be considered during decomposition. In silico experiments indicate that layout patterns that are printed by the trim mask may experience the highest levels of image distortion. Therefore, these patterns should be assisted by sidewalls of spacer patterns to improve printing robustness. Next, we present an integer linear programming-based decomposition method that avoids decomposition conflicts and sensitive trim edges simultaneously. To improve runtime and extend its application to partially decomposable layouts, too, a partitioning-based decomposition is also proposed. Our experiments reveal that the proposed methods decrease the total length of sensitive trim patterns and consequently reduce the total edge placement error significantly.

With the widespread adoption of design for manufacturing techniques and design and process co-optimization as well as the increase in the complexity of the processes to manufacture integrated circuits there is pressing need in finding quickly to calibrate yet accurate and high performing methods to identify layout topologies which may cause yield loss. While full-based simulations provide the most accurate prediction possible their runtime prohibits an adoption at all levels of the design flow. Alternative traditional rule checking including pattern matching techniques are fast but have a limited application in finding locations that were not part the training set. Several approaches to improve the accuracy of the prediction to reduce the number of miss structures and false detections have been proposed, but none have yielded and acceptable tradeoff between accuracy and runtime. This contest is aimed to provide a suite of layouts which highlight the challenges of this application: Widely different classes, limited amount of data and low prediction rates.

Under real and continuously improving manufacturing conditions, lithography hotspot detection faces several key challenges. First, real hotspots become less but harder to fix at post-layout stages; second, false alarm rate must be kept low to avoid excessive and expensive post-processing hotspot removal; third, full chip physical verification and optimization require fast turn-around time. To address these issues, we propose a high performance lithographic hotspot detection flow with ultra-fast speed and high fidelity. It consists of a novel set of hotspot signature definitions and a hierarchically refined detection flow with powerful machine learning kernels, ANN (artificial neural network) and SVM (support vector machine). We have implemented our algorithm with industry-strength engine under real manufacturing conditions in 45nm process, and showed that it significantly outperforms previous state-of-the-art algorithms in hotspot detection false alarm rate (2.4X to 2300X reduction) and simulation run-time (5X to 237X reduction), meanwhile archiving similar or slightly better hotspot detection accuracies. Such high performance lithographic hotspot detection under real manufacturing conditions is especially suitable for guiding lithography friendly physical design.

Printability of layout objects becomes increasingly dependent on neighboring shapes within a larger and larger context window. In this paper, we propose a two-level hotspot pattern classification methodology that examines both central and peripheral patterns. Accuracy and runtime enhancement techniques are proposed, making our detection methodology robust and efficient as a fast physical verification tool that can be applied during early design stages to large-scale designs. We position our method as an approximate detection solution, similar to pattern matching-based tools widely adopted by the industry. In addition, our analyses of classification results reveal that the majority of non-hotspots falsely predicted as hotspots have printed CD barely over the minimum allowable CD threshold. Our method is verified on several 45 nm and 32 nm industrial designs.

Under the real and evolving manufacturing conditions, lithography hotspot detection faces many challenges. First, real hotspots become hard to identify at early design stages and hard to fix at post-layout stages. Second, false alarms must be kept low to avoid excessive and expensive post-processing hotspot removal. Third, full chip physical verification and optimization require very fast turn-around time. Last but not least, rapid technology advancement favors generic hotspot detection methodologies to avoid exhaustive pattern enumeration and excessive development/update as technology evolves. To address the above issues, we propose a high performance hotspot detection methodology consisting of: 1) a fast layout analyzer; 2) powerful hotspot pattern identifiers; and 3) a generic and efficient flow with successive performance refinements. We implement our algorithms with industry-strength engine under real manufacturing conditions and show that it significantly outperforms state-of-the-art algorithms in false alarms (2.4X to 2300X reduction) and runtime (5X to 237X reduction), meanwhile achieving similar or better hotspot accuracies. Compared with pattern matching, our method achieves higher prediction accuracy for hotspots that are not previously characterized, therefore, more detection generality when exhaustive pattern enumeration is too expensive to perform a priori. Such high performance hotspot detection is especially suitable for lithography-friendly physical design.