Gas detection and environmental monitoring have become essential tasks to ensure the safety of people in many industries, such as mining, wastewater treatment plants, semiconductor manufacturing, and chemical manufacturers. To limit risk and keep people safe, it is necessary to monitor the environment where these gases could possibly be present and signal an alarm when a toxic or explosive condition may occur. This paper describes the implementation of a Low Power Wide Area Network (LPWAN) and the use of LoRa technology to design a cloud-based environmental and gas detection system. In the article, ESP32 microcontroller with integrated LoRa modules connected via SPI communication are used to wirelessly send various sensor readings back to the main controller, where dangerous situations will be announced. The various sensor readings include gas value, temperature, humidity, and some important diagnostic information from the end device to signal improper working conditions. Some of the sensors used in this project include electrochemical (gas) and capacitive (temperature and humidity) sensing elements. Since safety is the most important factor in these situations, if an unsafe condition is found, the device will set off an alarm immediately to communicate a problem for a safe evacuation protocol. Using LoRa technology, the data can be sent over large distances of over 1 kilometer to cover entire buildings with only one gateway/main controller, and low power consumption will require minimal maintenance and updates. The novel solution presented also offers real-time monitoring and predictive capabilities through cloud-enabled features and machine learning for a wider impact. Extensive testing and analysis of latency, power consumption, communication range, and reliability are presented along with practical guidelines.

A system was developed using a bagging (bootstrap-aggregating) ensemble of neural networks to classify time-series data with class imbalanced datasets. The proposed system uses a Data Balanced Bagging Ensemble (DBBE) of Convolutional-LSTM (CLSTM) Neural Networks (DBBE- CLSTM) to classify accelerometer and EEG datasets. The base neural network (CLSTM) that is used in the DBBE-CLSTM contains three convolutional layers with a batch normalization layer following each convolutional layer, one max-pooling layer, one LSTM layer, and one sigmoid classification layer. A bagging ensemble was created which used the CLSTM paired with the proposed data balancing technique as the ensemble's base learner. The proposed bagging ensemble achieves a validation set average accuracy of 90.42% and a validation set recall of 93.23% on an accelerometer dataset. Ultimately, the proposed DBBE- CLSTM achieves the best overall performance of the models developed in this paper when evaluating both accuracy and recall, with the DBBE-CLSTM achieving greater than 90% for both metrics. As a secondary verification of the proposed DBBE- CLSTM, we evaluated the model on the UCI Epileptic Seizure Detection dataset and show that the model achieved high performance across all evaluated metrics. The DBBE-CLSTM achieved an average validation set accuracy of 99.23%, and average validation set f1-score of 0.9809 on UCI Seizure dataset.

The growing trend in current complex embedded systems is to deploy a multiprocessor system-on-chip (MPSoC). A MPSoC consists of multiple heterogeneous processing elements, a memory hierarchy, and input/output components which are linked together by an on-chip interconnect structure. Such an architecture provides the flexibility to meet the performance requirements of multimedia applications while respecting the constraints on memory, cost, size, time, and power. Many embedded systems employ software-managed memories known as scratch-pad memories (SPM). Unlike caches, SPMs are software-controlled and hence the execution time of applications on such systems can be accurately predicted. Scheduling the tasks of an embedded application on the processors and partitioning the available SPM budget among these processors are two critical issues in such systems. Often, these are considered separately; such a decoupled approach may miss better quality schedules. In this paper, we present an integrated approach to task scheduling and SPM partitioning to further reduce the execution time of embedded applications. Results on several real-life benchmarks show the significant improvement from our proposed technique.

Most modern digital signal processors (DSPs) provide multiple address registers and a dedicated address generation unit (AGU) which performs address generation in parallel to instruction execution. There is no address computation overhead if the next address is within the auto-modify range. A careful placement of variables in memory is utilized to decrease the number of address arithmetic instructions and thus to generate compact and efficient code. The simple offset assignment (SOA) problem concerns the layout of variables for machines with one address register and the general offset assignment (GOA) deals with multiple address registers. Both these problems assume that each variable needs to be allocated for the entire duration of a program. Both SOA and GOA are NP-complete. In this article, we present effective heuristics for the simple and the general offset assignment problems with variable coalescing where two or more non-interfering variables can be mapped into the same memory location. Results on several benchmarks show the significant improvement of our proposed heuristics compared to other heuristics in the literature.

Digital Signal Processors (DSPs) are a family of embedded processors designed under tight memory, area, and cost constraints. Many DSPs use irregular addressing modes where base-plus-offset mode is not supported. However, they often have Address Generation Units (AGUs) that can perform auto-increment/decrement address arithmetic instructions in parallel with Load/Store instructions. This feature can be utilized to reduce the number of explicit address arithmetic instructions and thus reduce the embedded application code size. This code size reduction is essential for this family of DSP as the code usually resides in the ROM and hence the code size directly translates into silicon area. An effective technique for optimized code generation is offset assignment. This is a well-used technique in the literature to decrease the code size by finding an offset assignment that can effectively utilize auto-increment/decrement. This problem is known as simple offset assignment when there is only one address register and as General Offset Assignment (GOA) for multiple available address registers. In this article, we present an optimal Integer Linear Programming (ILP) solution to the offset assignment problem with variable coalescing where more than one variable can share the same memory location. Variable permutation is also formulated to find the best access sequence to achieve the best offset assignment that decreases the code size the most. Experimental results on several benchmarks show the effectiveness of our variable permutation technique as well as the large improvement from the ILP-based solutions compared to heuristics.

This paper presents an efficient method to determine minimum system-on-chip (SOC) test schedules with precedence and power constraints based on simulated annealing. The problem is solved using a partitioned testing scheme with run to completion that minimizes the number of idle test slots. The method can handle SOC test scheduling with and without power constraints in addition to precedence constraints that preserve desirable orderings among tests. We present experimental results for various SOC examples that demonstrate the effectiveness of the method. The method achieved optimal test schedules in all attempted cases in a short CPU time.