R. B. Steck

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dblp:71/1664 · DBLP profile ↗

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1ranked-venue papers

0as first author

0since 2021 · last 1986

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

1 paper

Electronic design automation · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

Topic	Papers	Last	Evidence papers
Electronic design automation hardware verification and test	1	1986	SCAT - a new statistical timing verifier in a silicon compiler system · DAC 1986
Electronic design automation physical design	1	1986	SCAT - a new statistical timing verifier in a silicon compiler system · DAC 1986
Electronic design automation › system-level design › system synthesis silicon compiler	1	1986	SCAT - a new statistical timing verifier in a silicon compiler system · DAC 1986
Electronic design automation › hardware verification and test › timing verification statistical timing verification	1	1986	SCAT - a new statistical timing verifier in a silicon compiler system · DAC 1986
Electronic design automation › hardware verification and test timing verification	1	1986	SCAT - a new statistical timing verifier in a silicon compiler system · DAC 1986

Methods — techniques the papers use, named apart from their topics

block-oriented statistical algorithms · 0.0

Year	Publication	Venue	Position
1986	SCAT - a new statistical timing verifier in a silicon compiler system abstract The program SCAT is a new timing verifier within the ALGIC silicon compiler. It provides a precise assessment of the timing behaviour of the automatically generated LSI circuits by means of block-oriented statistical algorithms leading to a running time approximately linear to the number of circuit elements, which are emulated by delay time elements. Interconnect delays are handled by the same statistical model. Synchronous circuits are described by an appropriate coordinate transformation leading to an algorithm for the calculation of the minimum clock period. The special case of recursive structures is briefly mentioned. Manfred Glesner, Johannes Schuck, R. B. Steck	DAC	3