On behalf of the Steering, Program and Organizing Committees, we would like to welcome you to the European Test Symposium 2016 (ETS'16); the largest event in Europe entirely devoted to presenting and discussing scientific trends, emerging results, hot topics, and applications in the area of electronic circuit and system testing. ETS'16 is the 21st edition of the symposium and is held in Amsterdam, The Netherlands. Amsterdam is the capital and most populous city of the Kingdom of the Netherlands. Amsterdam's name derives from Amstelredamme, indicative of the city's origin as a dam of the river Amstel.

Testing of Analogue/Mixed Signal ICs has reached a transition point. In the past AMS testing was based on functional tests that ensured that the analogue specifications were met. Unfortunately this approach is expensive; testing an `analogue' transistor can be 1000x more expensive than testing a digital transistor. What is even a bigger concern in industry is that a large fraction of the AMS test development takes place after first silicon. Digital blocks are up and running in hours while the AMS part typically takes days or weeks. As a result AMS test is in the critical path towards the customer. Hence, the specification-based functional-test approach is becoming very costly both from a test time point of view and from a test development point of view. Already for a number of years industry is exploring alternatives. In the tutorial a number of those alternatives are covered such as usages of DC measurements instead of dynamic measurements, BIST for AMS blocks, and structural test approaches. These approaches have the advantage that they enable shorter test times but also that it can be verified before tape-out, hence shifting the effort out of the critical path. The tutorial is concluded with an outlook on the future requirements that address a frame-work for fast verification, validation and characterization of AMS blocks and test requirements related to adaptive AMS blocks which adjust their performance over lifetime.

Summary form only given. The major bottleneck for technology scaling is the growing rate of hardware failures. Process variations are becoming extreme and sensitivity to radiation is becoming severe. In addition, intrinsic failures such as device parameter degradation are accelerating the wear-out. All of these are leading to higher random in-filed failures and shorter device lifetime. The 2011 ITRS (International Technology Roadmap for Semiconductors) projects very high bit failure rates of the order of 10-2for SRAM and of 10-3for latches for 16nm high performance technology. Hence, solving reliability challenges for future technologies requires new efficient and cost effective approaches not only to detect and recover from in-filed failures, but also to extend the device lifetime for targeted applications.

Accurate diagnosis of open defects is key to identifying process problems and achieving fast yield improvement. Current diagnosis methodologies for interconnect full open defects have demonstrated their efficiency, assuming that the defective line voltage is mainly determined by neighboring lines and downstream transistor parasitic capacitances. However, the continuous reduction of oxide thickness with every technology node increases gate leakage current significantly, even for high-kdielectrics. In this context, in nanometer CMOS technologies, the defective line cannot be assumed to be electrically isolated because of the impact of gate leakage currents, which may invalidate diagnosis results provided by present methodologies. In this paper, a new methodology is proposed to diagnose interconnect full open defects under the influence of gate leakage currents in CMOS technologies. To the authors' knowledge, such influence has not been previously considered by any of the existing methodologies. Simulation and experimental results demonstrate the proposal efficiency.

Power supply noise (PSN) has become a critical issue during high-quality at-speed testing. Discrepancies between the circuit's switching activity during functional and test mode can cause overtesting and lead to yield loss. Alternatively, reduced PSN effects around critical paths can result in undertesting the chip, causing test escapes. To achieve a high-quality at-speed test, it is necessary to solve these problems simultaneously. Our previous work introduced a noise index model (NIM), which can be used to predict the mismatch between expected and real path delays. This paper quantitatively investigates and compares NIM values for critical paths during functional and test mode. We then propose a test pattern modification method that harnesses the NIM. The method fills a subset of the don't care bits in partially specified test vectors such that the worst observed functional NIM for the targeted critical path is replicated during test mode.

We present an application of Defect Oriented Testing (DOT1) to an industrial mixed signal device to reduce test time and maintain quality. The device is an automotive IC product with stringent quality requirements and a mature test program that is already in volume production. A complete flow is presented including defect extraction, defect simulation, test selection, and validation. A major challenge of DOT for mixed signal devices is the simulation time. We address this challenge with a new fault simulation algorithm that provides significant speedup in the DOT process. Based on the fault simulations, we determine a minimal set of tests which detects all defects. The proposed minimal test set is compared with the actual test results of more than a million ICs. We prove that the production tests of the device can be reduced by at least 35%.

We present an application of Defect Oriented Testing (DOT) to an industrial mixed signal device to reduce test time and maintain quality. The device is an automotive IC product with stringent quality requirements and a mature test program that is already in volume production. A complete flow is presented including defect extraction, defect simulation, and test selection. A major challenge of DOT for mixed signal devices is the simulation time. We address this challenge with a new fault simulation algorithm that provides significant speedup of over 100x in the DOT process. Moreover, a number of methods are presented to improve the accuracy of this algorithm. Based on the fault simulations, we determine a minimal set of tests which detects all defects. The proposed minimal test set is compared with the actual test results of more than a million ICs. We prove that the analyzed production tests of the device can be reduced by at least 50%.

The development of accurate diagnosis methodologies is important to identify process problems and achieve fast yield improvement. As open defects are becoming dominant in some CMOS technologies, their accurate diagnosis is key to improving the quality of new very large-scale integrated circuits. Widely used interconnect full open diagnosis procedures are based on the assumption that neighboring lines determine the voltage of the defective line. However, this assumption decreases the diagnosis efficiency for opens in interconnect lines with fan-out, where the influence of transistor capacitances is significant. This paper presents a diagnosis methodology for interconnect full open defects which considers and models the impact of transistor parasitic capacitances on the defective node accurately. The methodology is able to properly diagnose interconnect opens with fan-out even in the presence of Byzantine behavior. Diagnosis results for real defective devices from different technology nodes are also provided.

An Interconnect full open defect breaks the connection between the driver and the gate terminals of downstream transistors, generating a floating line. The behavior of floating lines is known to depend on several factors, namely parasitic capacitances to neighboring structures, transistor capacitances of downstream gate(s) and trapped charges. For nanometer CMOS technologies, the reduction of oxide thickness leads to a significant increase in gate tunneling leakage. This new phenomenon influences the behavior of circuits with interconnect full open defects. Floating lines can no longer be considered electrically isolated and are subjected to transient evolutions, reaching a steady state determined by the technology, downstream interconnect and gate(s) topology. The occurrence of such defects and the impact of gate tunneling leakage are expected to increase in the future. In this work, interconnect full open defects affecting nanometer CMOS technologies are analyzed and the defective logic response of downstream gates after reaching the steady state is predicted. Experimental evidence of this behavior is presented for circuits belonging to a 180 nm and a 65 nm CMOS technologies. Technology trends show that the impact of gate leakage currents is expected to increase in future technologies.

As CMOS technology continues to scale, the accurate prediction of silicon timing through the use of pre-silicon modeling and analysis has become especially difficult. These timing mismatches are important because they make it hard to accurately design circuits that meet timing specifications at first-silicon. Among all the parameters leading to the timing discrepancy between simulation and silicon, this paper studies the effect of dynamic IR-drop on the delay of a path. We propose a noise index model, NIM, which can be used to predict the mismatch between expected and real path delays. The noise index considers both the proximity of switching activity to the path and physical characteristics of the design. To evaluate the method, we performed silicon measurements on randomly selected paths from an industrial 65 nm design and compared these with Spice simulations. We show that a very strong correlation exists between the noise index model and the deviations between simulations and silicon measurements.

The development of accurate diagnosis methodologies is important to solve process problems and achieve fast yield improvement. As open defects are common in CMOS technologies, accurate diagnosis of open defects becomes a key factor. Widely used interconnect full open diagnosis procedures are based on the assumption that neighbouring lines determine the voltage of the defective line. However, this assumption decreases the diagnosis efficiency for opens in interconnect lines with fan-out, when the influence of transistor capacitances becomes important. This work presents a diagnosis methodology for interconnect full open defects where the impact of transistor parasitic capacitances is included. The methodology is able to properly diagnose interconnect opens with fan-out even in the presence of Byzantine behaviour. Diagnosis results for real defective devices from different technology nodes are presented.

With test quality being an imperative, this paper presents a methodology on how to apply volume scan diagnosis - known from the field of yield learning - to the domain of test quality learning. Volume diagnosis allows to drastically accelerate the learning cycle. We give guidelines on how to improve test pattern generation strategies and try to answer which defects can be addressed deterministically with adequate fault models versus where probabilistic methods such as N-detect need be applied. The paper is based on a detailed analysis of scan diagnosis data from a production volume of well over one million devices of a 90 nm product.

Full open defects on interconnect lines cause broken wires to become floating. The voltage of a floating line depends on its topological characteristics, namely parasitic capacitances to neighbouring structures, transistor capacitances of the downstream gate(s) and trapped charge. However, in nanometer CMOS technologies gate oxide thickness is reduced below a few tens of A, resulting in the gate tunnelling leakage strongly influencing the behaviour of defective circuits with full open defects. Floating lines cannot be considered electrically isolated anymore and are subjected to transient evolutions until reaching a quiescent state, determined by the technology and the downstream gate(s). The occurrence of full opens as well as the impact of gate tunnelling leakage are expected to increase for future technologies. The transient response of full open defects on interconnect lines is analysed for nanometer technologies based on predictive technology models. A method to estimate the delay of defective circuits is proposed. Experimental evidence of this behaviour is presented for a test chip design of 0.18 mum technology.

Full open defects on the interconnect lines cause the broken wires to become floating. The voltage of a floating line depends on its topological characteristics, namely: parasitic capacitances to neighbouring structures, transistor capacitances of the downstream gate(s) and the trapped charge. However, in nanometric CMOS technologies, the oxide thickness is reduced below a few tens of Aring causing the gate tunnelling leakage to strongly impact the behaviour of defective circuits with full open defects. Floating lines can not be considered electrically isolated anymore and are subjected to transient evolutions until arriving at a quiescent state, determined by the technology and the downstream gate(s). The occurrence of full opens as well as the impact of the gate tunnelling leakage is expected to increase for future technologies. The analysis of full opens affecting basic CMOS gates is presented and their defective behaviour characterized. The prediction of the defective logic response of such basic gates is presented for nanometric technologies based on predictive technology models. The final steady state is found to be independent on the initial state of the floating node. Experimental evidence of this behaviour is presented for an industrial chip of 0.18 mum technology.

Improvement of diagnosis methodologies is a key factor for fast failure analysis and yield improvement. As bridging defects are a common defect type in CMOS circuits, diagnosing this class of defect becomes relevant for present and future technologies. Bridging defects cause two additional current components, the bridge and the downstream current. This work presents the effect of the downstream current on current signatures and its impact on the diagnosis of such defects. The authors demonstrate that the impact of downstream current is minimized at low power supply (Vdd) values. Therefore, current measurements at low power supply voltages are proposed to enhance bridge diagnosis. Experimental evidence of this behaviour is presented for real devices. Furthermore, current signatures measured at VVLVare used for the diagnosis of fifteen failing 0.18mum technology devices, which are demonstrated to contain a bridging defect.

Application specific ICs are typically designed to meet a given performance specification. For these ICs a higher performance does not add value and less performance makes the IC useless. This class of ICs is designed based on worst-case corner analysis. It is expected that this will become area costly in more advanced technologies. An alternative is to use statistical design techniques but this implies that the performance needs to be tested with, for example, path delay testing. Our experiments in 65 nm show that the actual delay depends on the global activity within an IC as well as effects in the local neighbourhood of the path. These global and local effects can independently cause about 15% of additional delay. Hence, their impact needs to be included during test and thr authors propose to create (close to) worst-case delay patterns. Individually, the patterns have an enhanced sensitivity for the most important local effects and combined they provide coverage for global effects. This makes them better suited as speed indicators than conventional path delay patterns.

A proposal for enhancing the diagnosis of full open defects in interconnecting lines of CMOS circuits is presented. The defective line is first classified as fully opened by means of a logic-based diagnosis tool (Faloc). The proposal is based on the division of the defective line into a number of segments. The selected group of segments is derived from the topology of the line and its surrounding circuitry. The logical information related to the neighbouring metal lines for each considered test pattern is taken into account. With the proposed diagnosis methodology, a set of likely locations for the open defect on the line is obtained. A ranking between the set of possible locations is presented based on the analysis of the quiescent current consumption of the circuit under test. Examples are presented in which the use of the diagnosis methodology is shown to discriminate between different locations of the full open defect.

The impact of test conditions on the detectability of open defects is investigated. We performed an inductive fault analysis on representative standard gates. The simulation results show that open-like defects result in a wide range of different voltage-delay dependencies, ranging from a strongly increasing to a strongly decreasing delay as a function of voltage. The behaviour is not only determined by the defect location but also by the test pattern. Knowing the expected behaviour of a certain defect location helps failure localisation. The detectability of a defect is strongly determined by the behaviour of the affected path as well as that of the longest path. Our simulations and measurements show that in general elevated supply voltages give a better detectability of open-like defects.

Excessive power supply noise can affect path delay and cause overkill during delay test. This paper presents low-cost noise models for fast power supply noise analysis and timing analysis considering noise impact. Our prior work only considered array-bond chips. This work proposes a noise analysis methodology that can be applied to wire-bond chips as well as array-bond chips. Experiments were performed on an industrial design. Silicon results show as much as a 15% delay variation due to different don't care fill approaches. The power supply noise impact on delay must be taken into account when delay tests are applied

This work proposes an effective method for applying fine-delay fault testing in order to improve defect coverage of especially resistive opens. The method is based on grouping conventional delay-fault patterns into sets of almost equal-length paths. This narrows the overall path length distribution and allows running the pattern sets at a higher speed, thus enabling the detection of small delay faults. These small delay faults are otherwise undetectable because they are masked by longer paths. A requirement for this method is to have hazard-free paths. To obtain these (almost) hazard-free paths we use a fast and simple postprocessing step that filters out paths with hazards. The experimental data shows the effectiveness and the necessity of this filtering process.

Defects due to process-design interaction have a systematic nature. Therefore they can have a profound impact on yield. The capability to detect (and correct) them is a requirement to continue to follow Moore's law. Most of the systematic defects are detected during the process development. These defects are detectable with test structures or visual inspection tools. However some process marginalities are only show-up in the topology of 'real' designs. Moreover, these defects are often not detectable with stuck-at testing. We show two examples of process related defects which could only be detected with more advanced test methods such as transition fault testing and low voltage testing. To correct systematic problems, however, one should not only have the capability to detect defects but also to identify them. Our examples show that other tests could have been far more sensitive in detecting systematic issues. Therefore the detection of systematic defects gives new requirements to test suites and can only be achieved with a shift in the position of manufacturing test.

New process technologies, increased design complexity, and more stringent customer quality requirements drive the need for better test quality, improved test program development, and faster ramp-up at overall lower product cost. In this paper we describe the main industry test trends and recent innovations in testing integrated circuits as they are applied within Philips.

Current-based tests are the most effective methods available to detect resistive shorts. Delta I DDQ testing is the most sensitive variant and can handle off-state currents of 10-100 mA of a single core. Nevertheless this is not sufficient to handle the next generations of very deep sub-micron technologies. Moreover delay-fault testing and very-low voltage testing are not a real alternative for the detection of resistive shorts. The main limitation of ΔI DDQ testing is the intra-die variation of the threshold voltage which results in variations in the off-state current. Two methods are investigated that improve the detection capabilities of ΔI DDQ testing. The first method reduces the impact of intra-die variation by reducing the amount of logic that switches states. This method can handle very large off-state currents although at the cost of a substantial increase in test time. The second method investigates the correct scaling of the intra-die variations as a function of temperature. We show that both methods improve the detection capabilities of ΔI DDQ testing. 1

I/sub DDQ/ testing is a well-known test method to filter dies with reliability risks. However, the test method is endangered by the increase in off-state current in advanced process technologies. An alternative for detecting resistive shorts is very-low voltage (VLV) testing. This test method tests dies at a strongly reduced supply voltage. The smaller the supply voltage, the higher the sensitivity for defects. This paper investigates if VLV testing can replace I/sub DDQ/ testing. To obtain a significant increase in defect coverage, one must use a supply voltage below 2/spl times/V/sub T/. In the experiments, a supply voltage of 1.5/spl times/V/sub T/ was used with relaxed timing. This makes the method more than twice as sensitive compared to 2/spl times/V/sub T/ and allows one to detect shorts with resistance of five times the detection limit at the nominal supply voltage. However, even with these settings we were only capable of detecting a small fraction of the I/sub DDQ/ anomalies. Therefore VLV is not suited to replace I/sub DDQ/ testing.

The increase in off-state current for deep submicron technologies will make conventional I/sub DDQ/ testing ineffective. An attractive alternative is differential I/sub DDQ/ or /spl Delta/I/sub DDQ/ testing as a function of the test pattern; it is relatively easy to implement it in a production environment and the method can detect I/sub DDQ/ anomalies of a few percent of the off-state current itself. In its simplest form the method is limited by state-dependent leakage current variations. More advanced versions of /spl Delta/I/sub DDQ/ testing can cope with these state-dependencies and are useful for off-state currents in the milliampere range. The presence of state-dependent leakage currents can be utilised to detect large passive defects, which are otherwise undetectable with /spl Delta/I/sub DDQ/. For even higher leak-age currents circuit-specific state-dependencies become the limiting factor and make /spl Delta/I/sub DDQ/ testing ineffective for devices with off-state currents above 100 mA.

Transient current testing (I/sub DDT/) has been often cited as an alternative and/or supplement to I/sub DDQ/ testing. The effectiveness of our I/sub DDT/ test method is compared with I/sub DDQ/ as well as with SA-based voltage testing for devices produced in 0.25 /spl mu/m technology. For these devices a large vector-to-vector spread in I/sub DDT/ is observed. This spread is investigated together with the die-to-die spread to determine a pass/fail criterion. The vector-to-vector spread is compensated by comparing the measured I/sub DDT/ values with those of a known good (golden) device. A hardware solution for an I/sub DDT/ monitor is presented which includes a correction for the golden device signature. Therefore real-time I/sub DDT/ testing on a digital tester without data-processing becomes feasible.