Chi-Chang Lin

dblp:71/1744 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1999
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Theory of computation · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 62% Reconfigurable computing and FPGAs · 38%
Theoretical computer science
1 paper
Coding theory · 100%

Topics — the 6 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › shared memory
distributed shared memory
0.011999
Proteus: A Runtime Reconfigurable Distributed Shared Memory System · HPDC 1999
Reconfigurable computing and FPGAs
dynamic reconfiguration
0.011999
Proteus: A Runtime Reconfigurable Distributed Shared Memory System · HPDC 1999
Memory systems
cache coherence
0.011999
Proteus: A Runtime Reconfigurable Distributed Shared Memory System · HPDC 1999
Memory systems
memory consistency
0.011999
Proteus: A Runtime Reconfigurable Distributed Shared Memory System · HPDC 1999
Coding theory › error-correcting codes
cyclic codes
0.011990
Computer search for binary cyclic UEP codes of odd length up to 65 · IEEE Trans. Inf. Theory 1990
Coding theory › error-correcting codes
unequal error protection codes
0.011990
Computer search for binary cyclic UEP codes of odd length up to 65 · IEEE Trans. Inf. Theory 1990

Methods — techniques the papers use, named apart from their topics

forced update · 0.0affinity page movement · 0.0adaptive workload redistribution · 0.0exhaustive computer search · 0.0analytic upper bound · 0.0
YearPublicationVenuePosition
1999 Proteus: A Runtime Reconfigurable Distributed Shared Memory System
abstract
This paper describes a Distributed Shared Memory (DSM) system called Proteus, which aims to support runtime node reconfiguration. To make the system execute efficiently after node reconfiguration and reduce the overhead of reconfiguration, Proteus employs an adaptive workload redistribution strategy to perform workload redistribution as well as an affinity page movement strategy to redistribute memory pages. Furthermore, a forced update technique and a set of scalable synchronization mechanisms are developed to keep memory consistent and to perform a correct synchronization, respectively.
Jyh-Chang Ueng, Ce-Kuen Shieh, Wu-Hwa Liu, Chi-Chang Lin
HPDC4
1990 Computer search for binary cyclic UEP codes of odd length up to 65
abstract
Exhaustive computation by a computer was used to find the unequal error protection capabilities of all binary cyclic codes of odd length up to 65 that have minimum distances of at least 3. For those codes for which upper bounds can only be computed on their unequal error protection capabilities, an analytic method developed by V.N. Dynkin and V.A. Togonidze (1976) is used to show that the upper bounds meet the exact unequal error protection capabilities.>
Mao Chao Lin, Chi-Chang Lin, Shu Lin 0001
IEEE Trans. Inf. Theory2