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Mike Davies 0002

dblp:71/1908-2 · DBLP profile ↗
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5ranked-venue papers
2as first author
3since 2021 · last 2024
0000-0002-5459-5957ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 2 · 1 first-author · 2 since 2021Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Emerging computing paradigms · 100%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%

Topics — the 8 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Emerging computing paradigms
neuromorphic computing
1.432022
Vector Symbolic Architectures as a Computing Framework for Emerging Hardware · Proc. IEEE 2022
Advancing Neuromorphic Computing With Loihi: A Survey of Results and Outlook · Proc. IEEE 2021
Mapping spiking neural networks onto a manycore neuromorphic architecture · PLDI 2018
Emerging computing paradigms › bio-inspired computing
vector symbolic architecture
0.612022
Vector Symbolic Architectures as a Computing Framework for Emerging Hardware · Proc. IEEE 2022
Emerging computing paradigms › neuromorphic hardware
spiking neural network hardware
0.512021
Advancing Neuromorphic Computing With Loihi: A Survey of Results and Outlook · Proc. IEEE 2021
Emerging computing paradigms › neuromorphic computing
synaptic plasticity
0.512021
Advancing Neuromorphic Computing With Loihi: A Survey of Results and Outlook · Proc. IEEE 2021
Emerging computing paradigms › neuromorphic computing
spiking neural network mapping
0.312018
Mapping spiking neural networks onto a manycore neuromorphic architecture · PLDI 2018
Emerging computing paradigms
neuromorphic hardware
0.222021
Advancing Neuromorphic Computing With Loihi: A Survey of Results and Outlook · Proc. IEEE 2021
Mapping spiking neural networks onto a manycore neuromorphic architecture · PLDI 2018
Emerging computing paradigms › neuromorphic computing
hyperdimensional computing
0.212022
Vector Symbolic Architectures as a Computing Framework for Emerging Hardware · Proc. IEEE 2022
Compilers and program optimization
deep learning compiler
0.112018
Mapping spiking neural networks onto a manycore neuromorphic architecture · PLDI 2018

Methods — techniques the papers use, named apart from their topics

greedy algorithm · 0.7spiking neural network · 0.5on-chip learning · 0.5
YearPublicationVenuePosition
2024 Efficient Video and Audio Processing with Loihi 2
abstract
Loihi 2 is an asynchronous, brain-inspired research processor that generalizes several fundamental elements of neuromorphic architecture, such as stateful neuron models communicating with event-driven spikes, in order to address limitations of the first generation Loihi. Here we explore and characterize some of these generalizations, such as sigma-delta encapsulation, resonate-and-fire neurons, and integer-valued spikes, as applied to standard video, audio, and signal processing tasks. We find that these new neuromorphic approaches can provide orders of magnitude gains in combined efficiency and latency (energy-delay-product) for feed-forward and convolutional neural networks applied to video, audio denoising, and spectral transforms compared to state-of-the-art solutions.
Sumit Bam Shrestha, Jonathan Timcheck, Edward Paxon Frady, Leobardo Campos-Macias, Mike Davies 0002
ICASSP5
2022 Vector Symbolic Architectures as a Computing Framework for Emerging Hardware
abstract
(also known as Hyperdimensional Computing). This framework is well suited for implementation in stochastic, emerging hardware and it naturally expresses the types of cognitive operations required for Artificial Intelligence (AI). We demonstrate in this article that the field-like algebraic structure of Vector Symbolic Architectures offers simple but powerful operations on high-dimensional vectors that can support all data structures and manipulations relevant to modern computing. In addition, we illustrate the distinguishing feature of Vector Symbolic Architectures, "computing in superposition," which sets it apart from conventional computing. It also opens the door to efficient solutions to the difficult combinatorial search problems inherent in AI applications. We sketch ways of demonstrating that Vector Symbolic Architectures are computationally universal. We see them acting as a framework for computing with distributed representations that can play a role of an abstraction layer for emerging computing hardware. This article serves as a reference for computer architects by illustrating the philosophy behind Vector Symbolic Architectures, techniques of distributed computing with them, and their relevance to emerging computing hardware, such as neuromorphic computing.
Denis Kleyko, Mike Davies 0002, Edward Paxon Frady, Pentti Kanerva, Spencer J. Kent, Bruno A. Olshausen, Evgeny Osipov, Jan M. Rabaey, Dmitri A. Rachkovskij, Abbas Rahimi, Friedrich T. Sommer
Proc. IEEE2
2021 Advancing Neuromorphic Computing With Loihi: A Survey of Results and Outlook
abstract
Deep artificial neural networks apply principles of the brain's information processing that led to breakthroughs in machine learning spanning many problem domains. Neuromorphic computing aims to take this a step further to chips more directly inspired by the form and function of biological neural circuits, so they can process new knowledge, adapt, behave, and learn in real time at low power levels. Despite several decades of research, until recently, very few published results have shown that today's neuromorphic chips can demonstrate quantitative computational value. This is now changing with the advent of Intel's Loihi, a neuromorphic research processor designed to support a broad range of spiking neural networks with sufficient scale, performance, and features to deliver competitive results compared to state-of-the-art contemporary computing architectures. This survey reviews results that are obtained to date with Loihi across the major algorithmic domains under study, including deep learning approaches and novel approaches that aim to more directly harness the key features of spike-based neuromorphic hardware. While conventional feedforward deep neural networks show modest if any benefit on Loihi, more brain-inspired networks using recurrence, precise spike-timing relationships, synaptic plasticity, stochasticity, and sparsity perform certain computation with orders of magnitude lower latency and energy compared to state-of-the-art conventional approaches. These compelling neuromorphic networks solve a diverse range of problems representative of brain-like computation, such as event-based data processing, adaptive control, constrained optimization, sparse feature regression, and graph search.
Mike Davies 0002, Andreas Wild, Garrick Orchard, Yulia Sandamirskaya, Gabriel A. Fonseca Guerra, Prasad Joshi, Philipp Plank, Sumedh R. Risbud
Proc. IEEE1
2018 Mapping spiking neural networks onto a manycore neuromorphic architecture
abstract
We present a compiler for Loihi, a novel manycore neuromorphic processor that features a programmable, on-chip learning engine for training and executing spiking neural networks (SNNs). An SNN is distinguished from other neural networks in that (1) its independent computing units, or "neurons", communicate with others only through spike messages; and (2) each neuron evaluates local learning rules, which are functions of spike arrival and departure timings, to modify its local state. The collective neuronal state dynamics of an SNN form a nonlinear dynamical system that can be cast as an unconventional model of computation. To realize such an SNN on Loihi requires each constituent neuron to locally store and independently update its own spike timing information. However, each Loihi core has limited resources for this purpose and these must be shared by neurons assigned to the same core. In this work, we present a compiler for Loihi that maps the neurons of an SNN onto and across Loihi's cores efficiently. We show that a poor neuron-to-core mapping can incur significant energy costs and address this with a greedy algorithm that compiles SNNs onto Loihi in a power-efficient manner. In so doing, we highlight the need for further development of compilers for this new, emerging class of architectures.
Chit-Kwan Lin, Andreas Wild, Gautham N. Chinya, Tsung-Han Lin, Mike Davies 0002
PLDI5
2011 One billion packet per second frame processing pipeline
Mike Davies 0002
Hot Chips Symposium1