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Yoshito Sakurai

dblp:71/2509 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1991
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Interconnection networks and networks-on-chip · 62% Integrated circuit design · 38%
Computer networks
1 paper
Internet architecture and protocols · 100%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Internet architecture and protocols › ATM networks
ATM switching		 0.011991
32 x 32 Shared Buffer Type ATM Switch VLSI's for B-ISDN's · IEEE J. Sel. Areas Commun. 1991
Internet architecture and protocols › ISDN
broadband ISDN		 0.011991
32 x 32 Shared Buffer Type ATM Switch VLSI's for B-ISDN's · IEEE J. Sel. Areas Commun. 1991
Interconnection networks and networks-on-chip › switch architecture
ATM switch		 0.011991
32 x 32 Shared Buffer Type ATM Switch VLSI's for B-ISDN's · IEEE J. Sel. Areas Commun. 1991
Integrated circuit design › VLSI design
CMOS VLSI		 0.011991
32 x 32 Shared Buffer Type ATM Switch VLSI's for B-ISDN's · IEEE J. Sel. Areas Commun. 1991
Interconnection networks and networks-on-chip
multicast		 0.011991
32 x 32 Shared Buffer Type ATM Switch VLSI's for B-ISDN's · IEEE J. Sel. Areas Commun. 1991
Interconnection networks and networks-on-chip
switch architecture		 0.011991
32 x 32 Shared Buffer Type ATM Switch VLSI's for B-ISDN's · IEEE J. Sel. Areas Commun. 1991

Methods — techniques the papers use, named apart from their topics

VLSI design · 0.0
YearPublicationVenuePosition
1991 32 x 32 Shared Buffer Type ATM Switch VLSI's for B-ISDN's
abstract
A set of 0.8 mu m CMOS VLSIs developed for shared buffer switches in asynchronous transfer mode (ATM) switching systems is described. A 32*32 unit switch consists of eight buffer memory VLSIs, two memory control VLSIs, and two commercially available first in first out (FIFO) memory LSIs. Using the VLSIs, the switch can be mounted on a printed board. To provide excellent traffic characteristics not only under random traffic conditions but also under burst traffic conditions, this switch has a 2-Mb shared buffer memory, the largest reported to date. which can save 4096 cells among 32 output ports. This switch has a priority control function to meet the different cell loss rate requirements and switching delay requirements of different service classes. A multicast function and a 600 Mb/s link switch architecture, which are suitable for ATM network systems connecting various media, and an expansion method using the 32*32 switching board to achieve large-scale switching systems such as 256*256 or 1024*1024 switches are discussed.>
Takahiko Kozaki, Noboru Endo, Yoshito Sakurai, Osamu Matsubara, Masao Mizukami, Ken'ichi Asano
 IEEE J. Sel. Areas Commun.3