A performance-driven global router for custom VLSI chip design, with the objective of maximizing the minimum delay slack, is presented. Resistances and capacitances of interconnections, input gate capacitances, and output driver resistance are used to approximate the interconnection delays during the routing. The router incrementally updates the delay at each sink pin of the signal obtained from the previous step during the routing. The maximum allowable delay at each sink pin (from a timing analyzer) along with the computer interconnection delays is used to guide the search process for the maximum-delay-slack route. It is shown that when the interconnection resistance is considered, minimizing the total net length is not always equivalent to minimizing the delay for a multiterminal net. The algorithm is experimentally shown to produce global routes achieving the objectives.>

A timing-driven global router is presented for custom chip design, whose objective is maximizing the minimum delay slack. Resistances and capacitances of interconnections, input gate capacitances and output driver resistance are used to approximate the interconnection delays during the routing. The router incrementally updates the delay at each sink pin of the signal obtained from the previous step during the routing. The maximum allowable delay at each sink pin (from a timing analyzer) along with the computed interconnection delays is used to guide the search process for the maximum-delay-slack route. It is shown that when the interconnection resistance is comparable to the output-driver resistance, minimizing the total net length is not always equivalent to minimizing the delay for a multiterminal net. The algorithm presented is experimentally shown to produce global routes achieving the objective.>

A procedure for path-delay constrained initial placement during chip floorplanning is presented which directly incorporates timing and geometrical constraints into the process. The problem is modeled and mathematically formulated as a constrained non-linear programming problem which is systematically divided and solved in three steps: timing minimization with module overlap, module separation and timing minimization without module overlap. To save computation time, two techniques for eliminating non-logical and noncritical paths are used to reduce the number of paths considered during the optimization. Experimental results show that the placement results satisfy all given timing and geometrical constraints, and have good total normalized wire delays.