Although innovations in manufacturing technology help in reducing variations, IC design variations are a fact of life. In addition to random variations, systematic stress induced variations are becoming increasingly important. This panel will bring the diverse views from academia, foundries, fabless and IDM communities to address various topics on next generation solutions for variability, with the main emphasis on design and architecture solutions. Specifically, this panel will discuss:• Would new architectures mitigate variability in 22nm and beyond?• Could design regularity effectively mitigate variability?• What design techniques can be used to minimize variability 'on-the-fly'?• What new techniques can be used for memories, register arrays and flip-flops?

In this paper, we investigate thermal via (T-via) planning during three-dimensional (3-D) floorplanning. First, we consider the temperature constrained T-via planning (TVP) problem on a given 3-D floorplan. Second, we integrate dynamic TVP into 3-D floorplanning process. Our main contribution and results can be summarized as follows. We solve the temperature constrained TVP problem by solving a sequence of simplified interlayer and intralayer TVP subproblems. Each subproblem is formulated as convex programming problem and we derive nearly optimal solution for detailed T-via distribution. Based on the TVP solution, we implement the integrated TVP and 3-D floorplanning algorithm in a two-stage approach. Before floorplanning, blocks are assigned into different layers by solving a sequence of knapsack problems. During floorplanning, T-vias are allocated with white space redistribution to optimize T-via insertion. Experimental results show that our TVP approach can reduce T-vias by 12% compared with a recent published work (J. Cong and Y. Zhang, "Thermal via planning for 3-D ICs," in Proc. Int. Conf. Comput.-Aided Des., Nov. 2005, pp.745-752). Compared with the postfloorplanning optimization approach, integrating TVP into floorplanning process can reduce T-vias by 16% with 21% runtime overhead

VLSI engineers have traditionally used a variety of CAD analysis tools (e.g. SPICE) to deal with variability.As we go into deep sub micron issues, the analysis is becoming harder due to many secondary effects becoming primary. Panelists will debate the variability trend and present the order of importance of many variability trends (Vdd, Vt, Interconnect, Leff, Gate Width) and their impact on design tools and methodologies.What new design tools, new modeling methodologies, and new (or old) design styles will combine to address variability?Will conservative design to accommodate variability halt the progress of Moore's Law?Is life as we know it over, or are we facing an opportunity for innovation in tools and design that will move us forward over the barriers that technology has placed in our path?.

Incorporating thermal vias into 3D ICs is a promising way to reduce circuit temperature by lowering down the thermal resistances between device layers. In this paper, we integrate dynamic thermal via planning into 3D floorplanning process. Our 3D floorplanning and thermal via planning approaches are implemented in a two-stage approach. Before floorplanning, the temperature-constrained vertical thermal via planning is formulated as a convex programming problem. Based on the analytical solution, blocks are assigned into different layers by solving a sequence of knapsack problems. Then a SA engine is used to generate floorplans of all these layers simultaneously. During floorplanning, thermal vias are distributed horizontally in each layer with white space redistribution to optimize thermal via insertion. Experimental results show that compared to a recent published result from [14], our method can reduce thermal vias by 15% with 38% runtime overhead.

New three-dimensional (3D) floorplanning and thermal via planning algorithms are proposed for thermal optimization in two-stacked die integration. Our contributions include (1) a two-stage design flow for 3D floorplanning, which scales down the enlarged solution space due to multidevice layer structure; (2) an efficient thermal-driven 3D floorplanning algorithm with power distribution constraints; (3) a thermal via planning algorithm considering congestion minimization. Experiments results show that our approach is nine times faster with better solution quality compared to a recent published result. In addition, the thermal via planning approach is proven to be very efficient to eliminate localized hot spots directly.

The notion of design for manufacturability is blurring the separation between the tasks of design and manufacture. In the era of nano-technologies, the description of the design rules has retreated back to an early stage form of many conditional cases and even an art. Thus, it is important to set the metrics for the manufacturability. However, who is going to be held accountable for the final outcomes? Should the designer, the EDA developer, the manufacture engineer, or a new breed of experts take the lead to tackle the problem?

DFM (Design for Manufacturability) has recently become a buzzword; it excites passion in semiconductor process, design, EDA and manufacturing circles. What is all this hype about?This tutorial reviews DFM, the ugly cousin of technology scaling, in a broad context, and includes both hard defects and parametric variations arising from manufacturing issues in its scope. It presents the various sources of the problem and their impact on yield, silicon vs. timing model correlation, mask cost, data size and time-to-market. It then presents design methodology and EDA tool solutions, both current and future, including restrictive design rules, preferred rules, layout fixes, design-manufacturing integration, lay-out-dependent modeling, variation-aware analysis and design.This tutorial is intended for engineers and project managers involved in design, EDA, OPC/RET/tapeout and design rule formulation.

In this paper, we expand our earlier neural network method for solving the scheduling problem in high level synthesis. The new algorithm, ANSA, operates in three phases. The first phase is a normalized mean field net algorithm with a new energy function which incorporates weighting of different operation types to create deeper basins of attraction. Other novelties include a fast and deterministic noise generation scheme and a new melting technique to determine the starting temperature. The next two stages provide a mechanism for finding nonuniformly distributed optimal schedules. The second phase uses the same energy function as the first but with a bias in favor of aligned operations. The third stage is a probabilistic correction algorithm for cases with highly irregular subschedules. ANSA was tested on five benchmark examples including large ones such as the discrete cosine transform for all possible schedule lengths with and without pipelining. It achieved a 100% convergence rate to optimal solutions in all cases.

Presents a distributed data-path synthesis approach which taps into the vast and cheap computing power of the distributed computing environments. The synthesis program is based on a novel approach where all processors simultaneously generate optimal schedules and allocate data-paths for them using a simple but powerful set of binding algorithms. The experimental results show that the distributed synthesis approach is very effective for exploring the design space.>

Traditional high-level synthesis systems generate a single schedule, and try to minimize the allocation cost for that schedule. Since there are often a large number of schedules for a given problem, this approach prematurely prunes the design space and it may miss many better solutions. The multi-schedule synthesis approach overcomes this deficiency by producing a number of schedules and generating a complete data-path for each schedule. In most cases multi-schedule synthesis not only produces better results but also runs faster than well-known synthesis systems such as HAL, SALSA, and SE.>

Circuit bipartitioning is an NP-hard combinatorial optimization problem in the layout synthesis of VLSI circuits, where we wish to find a partition of the circuit elements into two blocks such that the number of signal nets crossing the partition boundary is minimized. We have developed and experimented with several competitive learning neural network algorithms to solve this problem. The algorithms were tested on randomly generated circuits as well as several popular benchmark circuits. The stochastic reward and punishment neural network produced the best results which were comparable to those found by the Ratio Cut algorithm of Wei and Cheng.>

This paper describes a compiler and algorithms for simulation and fault diagnosis of computer hardware modeled in VHSIC Hardware Description Language(VHDL).Given a VHDL description, the compiler creates an internal representation.For simulation, a discrete-event based compiled code simulation algorithm is used.For fault diagnosis, a hierarchical approach using the stuck-at fault model at the first level and the arbitrary failure model at the second level, is used.The diagnosis algorithm reasons from first principles using constraint suspension.

This paper describes algorithms for fault diagnosis of computer hardware modeled in VHDL [1,2,3,4]. Given a VHDL description, the compiler creates an internal representation. For fault diagnosis, a hierarchical approach using the stuck-at fault model at the first level and the arbitrary failure model at the second level, is used. The diagnosis algorithm reasons from first principles using constraint suspension.

A parallel algorithm for symbolic compaction of two layered channels has been developed and implemented on the Connection Machine. It allows fast channel compaction with very little wasted space.

A massively parallel algorithm for fault simulation on the Connection Machine is presented. This algorithm achieves two to three orders of magnitude speedup over the one presented in [1]. The fault simulation methodology used here is combination of parallel fault simulation [2] and PPSFP [3]. Simulation rates of over 2.7 billion gate evaluations per second have been achieved.

A method is presented for simulation with two zillion and three values. The values that are propagated by the simulation include the familiar 0, 1, and X and also a collection of named unknowns and their formal negations. Each value fits into a single computer word. Applications of this restricted symbolic evaluation include design rule checking for circuits with embedded arrays and timing verification. The authors explore these two applications briefly. By carefully choosing rules for combining the two zillion and three values, and the representations of the values, it is possible to make simulation surprisingly efficient. The authors present two variants and an implementation of each. Both are fast; the faster one sometimes yields less information.>

A fast algorithm for fault simulation, using data-level parallelism, is presented for the Connection Machine. The algorithm is of the parallel pattern single-fault-propagation type. An implementation in C language has been completed and results are presented.>

The generation of a universal test set (UTS) for unate functions is used as a starting point. This test set is complete and minimal for the set of all unateness-preserving faults. However, for functions that are not unate in any variable, the UTS generated by this algorithm is the exhaustive set. An algorithm is presented that computes a good functional test set (GFTS) of reasonable size even for such functions. The algorithm does this by breaking up functions into more unate components, recursively computing GFTS for them, and combining the test sets in an appropriate way. The GFTS generated by the algorithm is compared to random test sets of the same size for gate-level fault coverage in typical implementations.>

We present a hybrid three-layer channel-routing algorithm that combines horizontal-vertical-horizontal (HVH) and vertical-horizontal-vertical (VHV) approaches [1]. The result is the best of both approaches. VHV excels when the vertical constraint graph (VCG) has long chains; HVH is strong when the VCG has a large number of incomparable nodes. In hybrid routing, the VCG is partitioned into two portions, one ideally suited for HVH and the other for VHV. The portions are routed with a transition track in between. It is shown that, for many channel-routing problems, the hybrid method can do with fewer tracks than the theoretical lower bounds of the algorithms given in [1][2][3]. A heuristic algorithm is given for determining an optimum partitioning into HVH and VHV portions. The algorithm is powerful and its performance on Deutsch's difficult example [8] is discussed as an illustration.

This correspondence presents a method for proof of correctness of register transfer level (RTL) parallel control sequences that describe hardware behavior. An RTL language endowed with parallel constructs is presented and its semantics is defined. The semantics includes temporal behavior. An assertion-based proof method is presented for verification of parallel control sequences described in this language. An example is given and comparisons are drawn between proofs of parallel register transfer level sequences and parallel programs. The temporal semantics associated with the language permits the construction and proof of parallel sequences that are not possible with parallel programs. Accessing shared resources outside critical regions is possible and is illustrated.

This paper extends Floyd's inductive assertion method to formal verification of register transfer level (RTL) hardware descriptions. An RTL description with imbedded assertions about machine state will be the input to the verifier. The formal semantics of an RTL language for synchronous designs are defined, to make mechanical generation of verification conditions (VC's) possible. These VC's are to be fed to a theorem prover. Proof of all the VC's constitutes complete verification. The semantic rules define how time advances, in addition to how machine variables change. These rules make possible verification of real-time performance as well as logical correctness. Such real-time performance verification is important for some hardware designs. The paper also emphasizes the differences between software and hardware verification. An example is given to illustrate the formal verification method.