Clock gating technology can reduce the consumption of clock signals' switching power of flip-flops. The clock gate enable functions can be identified by Boolean analysis of the logic inputs for all flip flops. However, the enable functions of clock gate can be further simplified, and the average number of flip flops driven by enable functions can be improved. In this way, the circuit area can be reduced; therefore, the clock gating can be improved and power saving can be achieved. This paper presents a technique for improving clock gating by optimizing the enable functions. The problem of improving clock gating is formulated as finding the optimal set of enable functions in the shared logic cone that leads to best power reduction on flip flops. First, enable functions are identified by random simulation and SAT. Then the optimal set of enable functions is found with partition method. This paper demonstrates the effectiveness of the approach through testing on MCNC benchmarks and industrial circuits. The experimental results show that the algorithm will get as much power saving as 3 times of that of the original clock gating circuits, and all benchmarks can run in tens of seconds.

Extended Finite State Machines (EFSMs) have been proposed to model control oriented systems. A version of this, with the data portion modeled by Presburger arithmetic, has been used in formal verification and test pattern generation. This paper proposes a general logic minimization scheme using don't care derived from both control and data path. It consists of methods to transfer don't cares through the data path and to generate logic don't cares from the data path using quantifier-free Presburger inequalities. Potential applications are discussed and preliminary results validate the scheme on reasonable examples.

Early power analysis for systems-on-chip (SoC) is crucial for determining the appropriate packaging and cost. This early analysis commonly relies on evaluating power formulas for all cores for multiple configurations of voltage, frequency, technology and application parameters, which is a tedious and error-prone process. This work presents a methodology and algorithms for automating the power analysis of SoCs. Given the power state machines for individual cores, this work defines the product power state machine for the whole SoC and uses formal symbolic simulation algorithms for traversing and computing the minimum and maximum power dissipated by sets of power states in the SoC.

Logic evaluation of a Boolean function or relation is traditionally done by simulating its gate-level implementation, or creating a branching program using its Binary Decision Diagram (BDD) representation, or using a set of look-up tables. We propose a new approach called generalized cofactoring diagrams, which are a generalization of the above methods. Algorithms are given for finding the optimal cofactoring structure for free-ordered BDD's and generalized cube cofactoring under an average path length (APL) cost criterion. Experiments on multi-valued functions show superior results to previously known methods by an average of 30%. The framework has direct applications in logic simulation, software synthesis for embedded control applications, and functional decomposition in logic synthesis.

This paper addresses the problem of automatic generation of implementation software from high-level functional specifications in the context of embedded system on chip designs. Software design complexity for embedded systems has increased so much that a high-level functional programming paradigm need to be adopted for formal verifiability, maintainability and short time-to-market. We propose a framework for efficiently generating implementation software from a synchronous state machine specification for embedded control systems. The framework is generic enough to allow hardware/software partition for a given architecture platform. It is demonstrated that the logic optimization and simulation techniques can be combined to produce fast execution code for such embedded systems. Specifically, we propose a framework for software synthesis from multi-valued logic, including fast evaluation of logic functions, and scheduling techniques for node execution. Experiments are performed to show the initial results of our algorithms in this framework.

We address optimizing multi-valued (MV) logic functions in a multi-level combinational logic network. Each node in the network, called an MV-node, has multi-valued inputs and single multi-valued output. The notion of don't cares used in binary logic is generalized to multi-valued logic. It contains two types of flexibility: incomplete specification and non-determinism. We generalize the computation of observability don't cares for a multi-valued function node. Methods are given to compute (a) the maximum set of observability don't cares, and (b) the compatible set of observability don't cares for each MV-node. We give a recursive image computation to transform the don't cares into the space of local inputs of the node to be minimized. The methods are applied to some experimental multi-valued networks, and demonstrate reduction in the size of the tables that represent multi-valued logic functions.