The authors present an extension of the automatic test pattern generation system SOCRATES to a hierarchical test pattern generation system for combinational and scan-based circuits. The proposed system is based on predefined high-level primitives, e.g., multiplexers and adders. The exploitation of high-level primitives leads to significant improvements in implication, unique sensitization, and multiple backtrace, all of which play a key role in the efficiency of any automatic test pattern generation (ATG) system. In order to perform deterministic ATG and fault simulation for internal faults of high-level primitives, the high-level primitives are dynamically expanded to their gate-level realization. A number of experimental results, achieved on circuits with several tens of thousands of primitives, demonstrate the efficiency of the proposed approach in terms of CPU time, fault coverage, and memory requirements.>

It is demonstrated that the exploitation of high-level primitives (HLPs) and, in particular, of the knowledge concerning their function in ATPG (automatic test pattern generation) leads to significant improvements in implication, unique sensitization, and multiple backtrace. Motivated by this observation and the necessity of covering all faults inside HLPs, the authors present the extension of the ATPG system SOCRATES to hierarchical test pattern generation, which is based upon HLPs and the strategy of dynamically expanding the HLPs to their gate-level realization, at most one at a time. Experimental results have substantiated that the proposed approach performs significantly better in terms of CPU time, elapsed time, fault coverage, and memory requirements than a gate-level ATPG algorithm. It is expected that the extended SOCRATES algorithm will be capable of coping with circuits consisting of 100000 gates and more within reasonable times, even in a workstation environment.>

An automatic test pattern generation system, SOCRATES, is presented. SOCRATES includes several novel concepts and techniques that significantly improve and accelerate the automatic test pattern generation process for combinational and scan-based circuits. Based on the FAN algorithm, improved implication, sensitization, and multiple backtrace procedures are described. The application of these techniques leads to a considerable reduction of the number of backtrackings and an earlier recognition of conflicts and redundancies. Several experiments using a set of combinational benchmark circuits demonstrate the efficiency of SOCRATES and its cost-effectiveness, even in a workstation environment.>