Multibit flip-flop (MBFF) banking has been widely adopted to reduce dynamic power, simplify clock tree structures, and minimize layout area. In our analysis, we reveal that early-stage banking, despite potential initial timing degradation, enables more extensive flip-flop merging, with subsequent placement refinements mitigating timing violations. Experimental results, benchmarked against the first-place winner from the 2024 ICCAD CAD Contest and most recent SOTA, demonstrate that our approach delivers competitive performance while providing enhanced design flexibility and superior power reduction.

In three-dimensional integrated circuits, the interconnection design among chiplets on redistribution layers (RDLs) is crucial for achieving high-performance computing systems. To optimize the inter-chip connections, most of the previous works focused on automatic signal net routing and pin assignment. The power/ground plane generation, is still a manual and time-consuming task, especially when generating the power planes of more than ten power supplies on a limited number of RDLs. This paper proposes a novel Voronoi diagram-based multiple power/ground plane generation methodology that simultaneously optimizes the power/ground planes of all power/ground nets by utilizing the white space of given RDLs, while considering the signal routing blockages, power integrity, and complex design rules. Experimental results show that the proposed approach can achieve not only optimal area utilization but also the best cross-layer power integrity in terms of the total number of redundant vias.

Analog placement is a crucial phase in analog integrated circuit synthesis, impacting the quality and performance of the final circuits. This process involves determining the physical positions of analog building blocks while minimizing chip area and interconnecting wire-length. Existing methodologies often rely on the simulated-annealing (SA) approach, prioritizing constraints like symmetry-island, proximity, and well-island. We present a novel reinforcement learning (RL) based analog placement methodology on the bounded-sliceline grid (BSG) structure. Introducing a hierarchical clustering feature in BSG, we address well-island, proximity, and symmetry constraints. In experimental comparisons with the SA approach, our RL-based method exhibits superior placement quality across various analog circuits.

This paper aims to estimate indoor occupancy given the real-time observed signals from the existing sensors; next, as a practical application, we build a dynamic control schedule for energy saving based on the estimated indoor occupancy. However, several issues need to be addressed. First, it is impossible to train the model with rich labels due to the expensive labeling cost. Second, manual annotation of the continuous occupancy rate is complex. Third, the mapping relationship between sensor data and occupancy will change in the long run. In this paper, we proposed a new algorithm named Self-Supervised Indoor Occupancy Estimation (SSIOE) to overcome the challenges. Specifically, our training scheme aims to (I) generate a set of pseudo labels in a simple way to mark the time periods believed to be either in a high or low occupancy state and (II) utilize these sparse labels for training a network to infer the continuous occupancy ratio. By reformulating the problem as a Wasserstein-distance-like estimation, SSIOE is a novel learning-based method that can rely only on the weak/sparse labels of either “high-occupancy” or “low-occupancy” and learn to estimate the continuous occupancy ratio. Furthermore, to deal with the scarce annotation problem, we proposed a novel physical constraint loss to model the physical prior. (III) Last but not least, to strengthen the adaptability, we integrated Model-Agnostic Meta-Learning (MAML) to train the model for dynamic model updating. Experimental results show that SSIOE can provide reliable occupancy estimation and flexibly adapt to various control modes without retraining the model.Note to Practitioners—This paper is motivated by the real-time occupancy estimation problem, which is crucial for building management systems to arrange lighting and air conditioning. A dynamic schedule adapted to the occupancy would help balance the user’s comfort and energy saving; however, installing the occupancy sensors raises additional costs. Therefore, this paper proposes SSIOE, a label-free machine learning algorithm that can learn to estimate the continuous occupancy ratio given the sensor status in real time. Prior works trained upon supervised machine learning methods suffer from heavy manual annotation workload, while the unsupervised machine learning approaches fail to provide continuous occupancy estimation values. This paper addresses the above challenges by proposing a novel self-supervised training scheme. Preliminary experiments suggest that this approach is feasible to work in real-world buildings. However, it should be noted that the occupancy estimated by SSIOE is a ratio (0.0-1.0), which is relative to the maximum and minimum occupancy of the training data (or fine-tuning data). For example, if the maximum number of occupants in the training data is 200 and the minimum number of occupants is 50, then the estimated occupancy value of 1.0 is about 200 occupants, and the occupancy value of 0.0 is about 50 occupants. When the maximum and minimum occupants of the space change, the model needs to be updated to capture the new mapping of the estimated occupancy ratio to the number of occupants. In future research, we plan to further improve and simplify the adaptation ability of SSIOE by continuously and automatically updating the system with the latest collected as the system runs.

Due to its excellent power efficiency, the successive-approximation-register (SAR) analog-to-digital converter (ADC) is an attractive design choice for low-power ADC implements. In analog layout design, the parasitics induced by interconnecting wires and elements affect the accuracy and performance of the device. Due to the requirement of low-power and high-speed, series of very small lateral metal-metal capacitor units are usually adopted as the architecture of capacitor array. Besides power consumption and area reduction, the parasitic capacitance would significantly affect the matching properties and settling time of capacitors. This work presents a framework to synthesize good-quality binary-weighted capacitors for custom SAR ADC. Also, this work proposes a parasitic-aware ILP-based weight-dynamic network routing algorithm to generate a layout considering parasitic capacitance and capacitance ratio mismatch simultaneously. The experimental result shows that the effective number of bits (ENOB) of the layout generated by our approach is comparable to or better than that of manual design and other automated works, closing the gap between pre-sim and post-sim results.

Aggressively monitoring and tracking system-on-chip (SoC) performance under process/voltage/temperature (PVT) variations is essential for high-performance computing systems. This work observes that different chips of the same SoC design may have different PVT-to-delay sensitivities, which must be carefully considered for accurate chip performance tracking. A learning-based method is then proposed to fit critical path delay for different chips with different PVT-to-delay sensitivities. Experimental results based on the fabricated chip samples of a 7nm SoC have justified the effectiveness of the proposed PVT-sensitive delay fitting method. Compared with the state-of-the-art, our method can achieve excellent performance tracking accuracy when the chip performance is dominated by different critical paths under different PVT conditions.

This article presents a new paradigm for analog placement, which further incorporates poles in addition to the considerations of symmetry island and monotonic current flow while minimizing wire crossings. The nodes along the signal paths in an analog circuit contribute to the poles, and the parasitics on these dominant poles can significantly limit the circuit performance. Although the monotonic placement methods introduced in the previous works can generate simpler routing topologies, the unawareness of poles, especially the dominant and the first non-dominant poles and wire crossings among critical nets, may increase wire load and performance degradation. This article proposes a pole-aware analog layout synthesis methodology to minimize the total wire load and wire crossings while satisfying different symmetry and topological routing constraints. Using a strong-connectivity approach to the group Steiner problem, the presented method for automatic selection of port locations can help reduce total wirelength, increase routing flexibility, and minimize total wire crossings. Experimental results show that the proposed approach results in better solution quality in circuit performance compared with other recent works.

Layout-dependent (LDEs) introduce an inevitable performance degradation in analog and mixed-signal circuit design with advanced process technologies below 90 nm. The main LDE sources, including the well proximity effect (WPE), length of diffusion (LOD), and the oxide-to-oxide spacing effect (OSE), cause substantial fluctuations in carrier mobility and threshold voltage of transistors. In traditional design flows, impact of these in post-layout simulation, leading to expensive re-design iterations by inspecting the physical locations of devices with respect to one another. In this article, we introduce the concept of an ideal mobility multiplier based on physics models, in order to minimize the LDE effects with a fast simulated annealing algorithm through various LDE alleviating operations. Based on the introduced mobility multiplier and the hierarchical B*-tree (HB*-tree) topological representation, our LDE-aware analog placement methodology can simultaneously optimize not only the area and wire length, but also the LDEs, while maintaining linear-packing time complexity of HB*-trees. Compared to the most recent works on 65 nm-based analog circuits, experimental results show that the proposed method can effectively and efficiently reduce LDE variations, while improving the circuit performance.

This paper presents an overview of common-centroid (CC) layout styles, used in analog designs to overcome the impact of systematic variations. CC layouts must be carefully engineered to minimize the impact of mismatch. Algorithms for CC layout must be aware of routing parasitics, layout-dependent effects (for active devices), and the performance impact of layout choices. The optimal CC layout further depends on factors such as the choice of the unit device and the relative impact of uncorrelated and systematic variations. The paper also examines scenarios where non-CC layouts may be preferable to CC layouts.

Complex universal logic gates, which may have higher density and flexibility than basic logic gates and look-up tables (LUT), are useful for cost-effective or security-oriented VLSI design requirements. However, most of the technology mapping algorithms aim to optimize combinational logic with basic standard cells or LUT components. It is desirable to investigate optimal technology mappers for complex universal gates in addition to basic standard cells and LUT components. This paper proposes a novel technology mapper for complex universal gates with a tight integration of the following techniques: Boolean network simulation with permutation classification, supergate library construction, dynamic programming based cut enumeration, Boolean matching with optimal universal cell covering. Experimental results show that the proposed method outperforms the state-of-the-art technology mapper in ABC, in terms of both area and delay.

Monitoring system-on-chip performance under process, voltage, and temperature (PVT) variations is very challenging, especially when the parasitic effects dominate the whole chip performance in advanced process nodes. Most of the previous works presented the performance monitoring methodologies based on known/predicted candidates of critical paths under different operating conditions. However, those methodologies may fail when the critical path is misrecognized or mispredicted. This paper proposes a novel machine-learning based chip performance monitoring methodology to accurately match the chip performance without requiring the information of critical paths under various PVT conditions. The experimental results based on measured chip performance show that the proposed methodology can achieve 98.5% accuracy in the worst case under wide-range PVT variations.

This paper presents a new paradigm for analog placement, which further incorporates poles in addition to the considerations of symmetry-island and monotonic current flow while minimizing wire crossings. The nodes along the signal path in an analog circuit contribute to the poles, and the parasitics on these dominant poles can significantly limit the circuit performance. Although the monotonic placements introduced in the previous works can generate simpler routing topologies, the unawareness of poles, especially both dominant pole and the first non-dominant pole, and wire crossing among critical nets may result in the increase wire-load and performance degradation. Experimental results show that the proposed pole-aware analog placement method considering symmetry-island, monotonic current flow, and crossing-wire minimization results in much better solution quality in terms of circuit performance.

This paper introduces the first problem formulation in the literature for automatic MOM capacitor cell generation with adaptive capacitance. Given an expected capacitance value and available metal layers, the proposed capacitor cell generation method can produce a compact MOM capacitor cell with minimized area and matched capacitance. Compared with MOM capacitor cells with non-adaptive capacitance in the previous work, the experimental results show that the proposed adaptive MOM capacitor cell generation method can reduce 25% chip area and 20% power consumption of the capacitor network in successive-approximation-register analog-to-digital converters (SAR ADC).

Analog IC designers and design houses have been accumulating their own design knowledge and constructing their own analog design repositories, including various design specifications, applications, and process technologies. As most of the analog layouts are handcrafted art works, different designers/companies may have different layout guidelines and preferences. When generating a new layout for certain analog design which already exists or is similar to any of those in the repositories, but with different circuit parameters or process technology files, applying layout migration is usually more preferable than starting from scratch. This paper introduces a holistic framework and new layout generation methodology to achieve analog layout integrity through learning and migration. The introduced methodology can effectively and efficiently preserve the preferences of placement and routing topologies from legacy layouts to new ones.

The "CAD Contest at ICCAD" is a challenging, multi-month, research and development competition, focusing on advanced, real-world problems in the field of electronic design automation (EDA). Since 2012, the contest has been publishing many sophisticated circuit design problems, from system-level design to physical design, together with industrial benchmarks and solution evaluators. Contestants can participate in one or more problems provided by EDA/IC industry. The winners will be awarded at an ICCAD special session dedicated to this contest. Every year, the contest attracts more than a hundred teams, fosters productive industry-academia collaborations, and leads to hundreds of publications in top-tier conferences and journals. The 2020 CAD Contest hits a record high of 186 teams from all over the world, which represents more than 50% growth compared to last year. The contest keeps enhancing impact and boosting EDA research.

Engineering change orders (ECOs) are pervasively applied to modern physical design of nanometer integrated circuits for cost-effective design changes. After applying ECO, a net may become open, which results in a large number of disconnected net components. Each net component further consists of a set of connected net shapes and vias on different layers. It is very challenging to efficiently and effectively identify all disconnected net components and find an obstacle-avoiding minimal-cost routing path among those net components. This paper introduces an open-net finder and an open-net connector based on the corner-stitching data structure for open-net routing, and proposes a new method of constructing a multilayer obstacle-avoiding component-to-component rectilinear minimum spanning tree. The preliminary idea and implementation of the proposed method had received the first place award in ICCAD-2017 CAD contest. This paper further details the complete idea of the proposed method. Experimental results show that the proposed open-net finder and connector outperform the top three open-net routers in the ICCAD-2017 CAD contest and two latest published works, with better routing costs and much shorter runtime.

Modern mixed-signal design usually contains multiple power signals with different supply voltages driving different sets of mixed-signal circuit blocks. As the process technology advances to nanometer era, IR drop becomes very significant, which may have great impact on circuit performance and reliability. Insufficient power supply to a circuit block will lead to performance degradation or even functional failure. Although such IR-drop problem can be minimized by widening metal wires or applying mesh routing structures of the power network, excessive metal usage of those power nets with different supply voltages will significantly increase both chip area and cost. This paper presents a new IR-aware routing method to simultaneously route multiple power nets in a mixed-signal design with the considerations of routing congestion, routing tree splitting, wire tapering, and metal layer optimization. Experimental results show that the presented method can effectively reduce total metal usage and satisfy IR-drop constraints.

The “CAD Contest at ICCAD” is a challenging, multi-month, research and development competition, focusing on advanced, real-world problems in the field of electronic design automation (EDA). Since 2012, the contest has published many sophisticated circuit design problems, from system-level design to physical design, together with industrial benchmarks and solution evaluators. Contestants can participate in one or more problems provided by EDA/IC industry. The winners will be awarded at an ICCAD special session dedicated to this contest. Every year, the contest attracts more than a hundred teams, fosters productive industry-academia collaborations, and leads to hundreds of publications in top-tier conferences and journals. The contest keeps enhancing impact and boosting EDA research.

Engineering Change Orders (ECO) modify a synthesized netlist after its specification has changed. ECO is divided into two major tasks: finding target signals whose functions should be updated and synthesizing the patch that produces the desired change. This paper proposes an efficient SAT-based solution for the second task: resource-aware computation of multi-output patch functions. The solution is based on several new algorithms and outperforms the top three winners of the 2017 ICCAD CAD Contest (Problem A).

Detecting equivalence classes of injected faults for functional verification of electronic systems is an important task because it helps reducing the number of faults to qualify a verification environment, and hence, improves the performance of qualification process and the validation time required for large-scale electronic systems. This paper describes an efficient way of detecting equivalent injected faults in a mapped netlist in order to speedup the qualification process of a verification environment for functional safety. The presented fault models include general faults resulting in arbitrary functional changes, in addition to conventional stuck-at faults. The solution is based on structural pruning and functional analysis performed by a synergistic combination of iterative Boolean satisfiability and guided simulation. It should be noted that traditional brute-force-like methods would take many hours or even days to identify thousands of equivalent functional faults injected to a small circuit with only hundred of cells. The proposed approach can achieve excellent fault reduction ratios within few seconds for such small circuits. The implementation also scales well for the largest ISCAS'89 and OpenCores benchmarks containing over 35K gates and 490K general functional faults.

The design of capacitor structures have great impact on capacitance density, parasitic capacitance, routability, and matching quality of capacitor network in a SAR ADC, which may affect power, performance, and area of the whole data converter. Most of the recent studies focused on common-centroid placement and routing optimization of the capacitor network. Only few of them investigated the structures of highly integrated capacitors. In this paper, a novel mortise-tenon metal-oxide-metal capacitor structure is proposed, which has the advantages of high capacitance density and small parasitic capacitance. Based on the proposed structure, an integer-linear-programming based capacitor sizing and routing parasitic matching method is further introduced. Experimental results show that the proposed structure and method can achieve the best capacitance density and matching quality of the capacitor network in a SAR ADC.

Retention registers/latches are commonly applied to power-gated circuits for state retention during the sleep mode. Recent studies have shown that applying uniform multi-bit retention registers (MBRRs) can reduce the storage size, and hence save more chip area and leakage power compared with single-bit retention registers. In this paper, a new problem formulation of power-gated circuit optimization with nonuniform MBRRs is studied for achieving even more storage saving and higher storage utilization. An ILP-based approach is proposed to effectively explore different combinations of nonuniform MBRR replacement. Experiment results show that the proposed approach can reduce 36% storage size, compared with the state-of-the-art uniform MBRR replacement, while achieving 100% storage utilization.

Capacitor sizing is a crucial step when designing charge-scaling digital-to-analog converters (DACs). Larger capacitor size can achieve better circuit accuracy and performance due to less impact from process gradient, parasitic mismatch, and local variation. However, it also results in larger chip area and higher power consumption. The size of binary-weighted capacitors in charge-scaling DACs is highly sensitive to the routing parasitics. Unmatched routing parasitics among binary-weighted capacitors will lead to large capacitor size for satisfying circuit accuracy and performance. Previous work focuses on the study of generating high-quality common-centroid placement of unit capacitor arrays while ignoring routing parasitics. None of them address the sizing of binary-weighed capacitors. This paper presents the first problem formulation in the literature which simultaneously considers capacitor sizing and parasitic matching during common-centroid capacitor layout generation such that the power consumption is minimized while the circuit accuracy/performance is also satisfied. Experimental results show that the proposed approach can achieve very significant chip area and power reductions compared with the state-of-the-art approaches.

With advancing process technologies and booming Internet of Things markets, millimeter-wave CMOS RFICs have evolved rapidly and been widely applied in recent years. The performance of CMOS RFICs is very sensitive to the chip layout, and a tiny variation of the microstrip length can cause a large impact to the circuit performance. This results in a time-consuming tuning process including much simulation effort for chip design, which becomes the major bottleneck for time to market. This paper introduces a progressive integer-linear-programming-based method consisting of two phases: 1) global layout generation and 2) iterative validation. In the global layout generation phase, we focus on the most critical constraints such as layout planarity and device connection relations to determine the topology of the final design. This provides a basis for constructing the accurate model in the iterative validation phase. The layouts generated by applying our method can satisfy very stringent routing requirements of microstrip lines, including spacing/noncrossing rules, precise length, and bend number minimization, within a given layout area. The resulting RFIC layouts excel in both performance and area with much fewer bends compared with the simulation-tuning based manual layout, while the layout generation time is significantly reduced from weeks to a few minutes.

As technology advances, smaller feature size enables layout precision in the lateral direction. In contrast to traditional metal-insulator-metal capacitors, metal-oxide-metal (MOM) capacitors are generally of higher density and consume less area, because they adopt a 3-D topology over several metal layers to use lateral field capacitance. To achieve little area consumption, MOM capacitors require new layout methods with routing even before placement. Since the routing wires are of comparable size to unit capacitors in MOM design, routing-induced parasitic capacitance must also be considered. To obtain a higher yield, common-centroid layout style and high dispersion of cells are desired. This paper introduces a new vertical bars structure for binary weighted MOM capacitor arrays and presents a new method to generate common-centroid regular-structured layouts with mismatch reduction and routing-parasitic-matching consideration. Experimental results show that the presented approach generates high-density, low-powered, and highly accurate ratioed capacitors.

Analog and mixed-signal integrated circuits play an important role in many modern emerging system-on-chip (SoC) design applications. With the expansion of the markets of those applications, the demands of analog/mixed-signal ICs have been dramatically increased. Although analog/mixed-signal ICs have gained more and more importance and demands in modern SoC applications, the development of analog electronic design automation (EDA) tools is still farther behind that of digital EDA tools. As a result, analog/mixed-signal IC design, especially the analog layout design, is still a manual, time-consuming, and error-prone task. In order to speed up modern SoC design for large varieties of emerging applications, it is desirable to develop novel analog/mixed-signal IC deign methodologies and algorithms, as well as new analog EDA tools. The purpose of this paper is to summarize recent research progress during the past decade, address new analog layout design challenges in advanced technology nodes, and facilitate more research activities in analog layout synthesis.

With advancing process technologies and booming IoT markets, millimeter-wave CMOS RFICs have been widely developed in recent years. Since the performance of CMOS RFICs is very sensitive to the precision of the layout, precise placement of devices and precisely matched microstrip lengths to given values have been a labor-intensive and time-consuming task, and thus become a major bottleneck for time to market. This paper introduces a progressive integer-linear-programming-based method to generate high-quality RFIC layouts satisfying very stringent routing requirements of microstrip lines, including spacing/non-crossing rules, precise length, and bend number minimization, within a given layout area. The resulting RFIC layouts excel in both performance and area with much fewer bends compared with the simulation-tuning based manual layout, while the layout generation time is significantly reduced from weeks to half an hour.

With shrinking process technology, decreasing supply voltage, and increasing clock frequency, noise reduction becomes more and more crucial to the success of modern mixed-signal system-on-chip design. To eliminate the switching noise due to crosstalk coupling between analog and digital signals, it is essential to fully separate the routing paths of analog and digital nets when generating mixed-signal layouts. Different from previous works which cannot fully separate analog and digital routing paths, this paper presents a novel hierarchical deterministic mixed-signal layout synthesis approach with the separation of analog and digital signal paths for switching noise elimination. Experimental results based on a third-order Σ Δ modulator show that the proposed approach can result in various layouts with separated analog and digital signal paths while achieving better signal-to-noise and distortion ratio, and overall performance specifications.

The FinFET technology is regarded as a better alternative for modern high-performance and low-power integrated-circuit design due to more effective channel control and lower power consumption. However, the gate-misalignment problem resulting from process variation and the parasitic resistance resulting from interconnecting wires based on the FinFET technology becomes even more severe compared with the conventional planar CMOS technology. Such gate misalignment and unwanted parasitic resistance may increase the threshold voltage and decrease the drain current of transistors. When applying the FinFET technology to analog circuit design, the variation of drain currents can destroy current-ratio matching among transistors and degrade circuit performance. In this article, we present the first FinFET placement and routing algorithms for layout generation of a common-centroid FinFET array to precisely match the current ratios among transistors. Experimental results show that the proposed matching-driven FinFET placement and routing algorithms can obtain the best current-ratio matching compared with the state-of-the-art common-centroid placer.

The FinFET technology has been regarded as a better alternative among different device technologies at 22nm node and beyond due to more effective channel control and lower power consumption. However, the gate misalignment problem resulting from process variation based on the FinFET technology becomes even severer compared with the conventional planar CMOS technology. Such misalignment may increase the threshold voltage and decrease the drain current of a single transistor. When applying the FinFET technology to analog circuit design, the variation of drain currents will destroy the current matching among transistors and degrade the circuit performance. In this paper, we present the first FinFET placement technique for analog circuits considering the impact of gate misalignment together with systematic and random mismatch. Experimental results show that the proposed algorithms can obtain an optimized common-centroid FinFET placement with much better current matching.

Utilizing multibit flip-flops (MBFFs) is one of the most effective power optimization techniques in modern nanometer integrated circuit design. Most of the previous works apply MBFFs without doing placement refinement of combinational logic cells. Such problem formulation may result in less power reduction due to tight timing constraints with fixed combinational logic cells. This paper introduces a novel placement flow with clock-tree aware flip-flop (FF) merging and MBFF generation, and proposes the corresponding algorithms to simultaneously minimize FF power and clock latency when applying MBFFs during placement. Experimental results based on the IWLS-2005 benchmark show that our approach is very effective in not only FF power but also clock latency minimization without degrading circuit performance. To our best knowledge, this is also the first work in the literature which considers clock trees when generating MBFFs during placement.

Analog layout design has been a manual, time-consuming, and error-prone task for decades. To speed up layout design time for a new design, analog layout designers prefer referring to legacy designs and layouts rather than starting from scratch, or thoroughly applying placement and routing tools because legacy layouts contain pretty much design expertise. Motivated by such layout design process, this paper presents the first knowledge-based physical synthesis methodology to generate new layouts by integrating existent design expertise. The proposed approach can automatically analyze legacy design data including circuits, layouts, and constraints, extract matched sub-circuits between new and legacy designs, and generate multiple layouts for the new design by utilizing the quality-approved legacy layouts as much as possible. Experimental results show that the proposed methodology can achieve high layout reusage rate, and hence the designers' layout preference can be successfully reserved.

Capacitor sizing is a crucial step when designing a charge-scaling digital-to-analog converter. Larger capacitor size can achieve better circuit accuracy and performance due to less impact from random, systematic, and parasitic mismatch. However, it also results in much larger chip area and even more power consumption. In addition to minimizing random and systematic mismatch during common-centroid capacitor placement, this paper presents the first problem formulation in the literature which simultaneously considers capacitor sizing and parasitic matching during common-centroid capacitor layout generation such that the power consumption is minimized while the circuit accuracy/performance is also satisfied. Experimental results show that the proposed approach can achieve very significant chip area and power reductions compared with the state of the art.

Applying retention registers is one of the most effective and efficient approaches to keep flip-flop states in power-gated circuits during the sleep mode. Instead of replacing each flip-flop in a power-gated circuit with a single-bit retention register (SBRR), recent research has shown that applying multi-bit retention registers (MBRRs) can effectively reduce the storage size, and hence save more chip area and leakage power. However, the previous work simply adopted greedy heuristics for power-gated circuit optimization with MBRRs, which first break feedback paths and then iteratively replace a flip-flop covering the maximum number of (k-1)-link paths with a k-bit retention register. Different from the previous work, this paper presents an even more effective approach based on integer-linear-programming (ILP) formulation with simultaneous consideration of all feedback paths. Experimental results show that the proposed approach can further reduce up to 46% storage size compared with the previous work.

Applying clock gates (CGs) and multi-bit flip-flops (MBFFs) are two of the most effective techniques for low power clock network design. Some previous works had proposed to optimize clock network with either CGs or MBFFs, but none of them simultaneously considers both CGs and MBFFs during clock network optimization. Although CGs and MBFFs can be optimized separately, the resulting dynamic power may not be optimal. This paper presents the first problem formulation in the literature for gated clock network optimization with simultaneous CG cloning and FF merging. To effectively solve the problem, a novel optimization flow consisting of MBFF-aware CG cloning, CG-based FF merging, and MBFF and CG placement optimization is introduced. Experimental results show that the proposed flow results in better dynamic power and clock wirelength compared with other flows which optimize gated clock network with CGs and MBFFs separately.

Although modern analog placement algorithms aimed to minimize area and wirelength while satisfying symmetry, proximity, and other placement constraints, the generated layout does not reflect the circuit performance very well because of the routing-induced parasitics on the critical current/signal paths. To simultaneously consider symmetry, wirelength, area utilization, and current/signal paths during analog placement, this paper explores the feasibilities of symmetry islands and monotonic current paths in slicing trees for analog placement optimization. Experimental results show that the proposed formulation and algorithms can generate much more compact layouts resulting in similar or even better circuit performance compared with the previous work.

Utilizing multi-bit flip-flops (MBFFs) is one of the most effective power optimization techniques in modern nanometer integrated circuit (IC) design. Most of the previous work apply MBFFs without doing placement refinement of combinational logic cells. Such problem formulation may result in less power reduction due to tight timing constraints with fixed combinational logic cells. This paper introduces a novel placement flow with clock-tree aware flip-flop merging and MBFF generation, and proposes the corresponding algorithms to simultaneously minimize flip-flop power and clock latency when applying MBFFs during placement. Experimental results based on the IWLS-2005 benchmark show that our approach is very effective in not only flip-flop power but also clock latency minimization without degrading circuit performance. To our best knowledge, this is also the first work in the literature which considers clock trees during flip-flop merging and MBFF generation.

In analog layout design, the accuracy of capacitance ratios correlates closely with both the matching properties among the ratioed capacitors and the induced parasitics due to interconnecting wires. However, most of the previous works only emphasized the matching properties of a common-centroid placement, but ignored the induced parasitics after it is routed. This paper addresses the parasitic issue in addition to device matching during common-centroid capacitor layout generation. To effectively minimize the routing-induced parasitics, a novel common-centroid placement style, distributed connected unit capacitors, is presented. Based on the placement style, the ratioed capacitor layout generation flow and algorithms are proposed to simultaneously optimize the matching properties of a common-centroid placement and minimize the induced parasitics. Experimental results show that the proposed approach can greatly reduce area, wirelength, and routing-induced parasitics, and guarantee the best matching quality after routing.

As process technologies advance to the subwavelength era, the 1-D design style is regarded as one of the most effective ways to continue scaling down the minimum feature size. To improve the printability of 1-D cell design, it is essential to insert dummy patterns and optimize line-end gap distribution for each layer. This paper presents novel 1-D cell generation algorithms that simultaneously minimize 1-D cell area and enhance the printability. Experimental results show that the proposed algorithms can effectively and efficiently reduce the number of diffusion gaps, minimize used routing tracks, insert sufficient dummy patterns, and eliminate stage-like line-end gaps without power and timing overhead. Consequently, the 1-D cell area is minimized and the printability of the cell is enhanced. To the best of our knowledge, this is also the first work in the literature that considers line-end gap distribution during 1-D cell generation.

Applying multi-bit flip-flops (MBFFs) for clock power reduction in modern nanometer ICs has been becoming a promising lower-power design technique. Many previous works tried to utilize as more MBFFs with larger bit numbers as possible to gain more clock power saving. However, an MBFF with a larger bit number may lead to serious crosstalk due to the close interconnecting wires belonging to different signal nets which are connected to the same MBFF. To address the problem, this paper analyzes, evaluates, and compares the relationship between power consumption and crosstalk when applying MBFFs with different bit numbers. To solve the addressed problem, a novel crosstalk-aware power optimization approach is further proposed to optimize power consumption while satisfying the crosstalk constraint. Experimental results show that the proposed approach is very effective in crosstalk avoidance when applying MBFFs for power optimization. To our best knowledge, this is also the first work in the literature that considers the crosstalk effect for the MBFF application.

Although modern analog placement algorithms aimed to minimize area and wirelength while satisfying symmetry, proximity, and other placement constraints, the generated layout does not reflect the circuit performance very well because of the routing-induced parasitics on the critical current/signal paths. This paper introduces the current-path constraints in analog placement, demonstrates their impact on circuit performance, and derives new problem formulation and algorithms to find placement solutions with monotonic current paths. Experimental results show that the proposed formulation and algorithms can generate compact layouts resulting in the even better circuit performance after performing post-layout simulation.

Modern circuit placement, especially analog placement, often needs to consider various constraints, such as symmetry, proximity, preplaced, variant, fixed-boundary, minimum separation, boundary, and fixed-outline constraints, for better electrical effects and higher performance. To handle these diverse constraints, topological floorplan representations are pervasively used because of their higher flexibility and smaller solution space. Due to their intrinsic limitation in deriving module adjacency information directly from the representations themselves, however, they might incur difficulties in handling related constraints. In this paper, we work on B*-trees, which have been shown to be most effective and efficient for floor-plan/placement problems, and present a corner stitching compliant B*-tree (CB-tree, for short) to remedy the significant deficiency in its module adjacency handling. A CB-tree is a B*-tree integrated with modified corner stitching to offer much higher flexibility/efficiency, especially for adjacent module identification/packing. Compared with the previous works, CB-trees can achieve the lowest time complexity for module packing with the aforementioned constraints. Experimental results show that the CB-trees achieve the best solution quality and consume the least running time for industrial designs with various constraints. In particular, our work provides key insights into the handling of comprehensive placement constraints with a topological representation.

Optimization for power is always one of the most important design objectives in modern nanometer integrated circuit design. Recent studies have shown the effectiveness of applying multi-bit flip-flops to save the power consumption of the clock network. This paper presents: 1) a novel design methodology of applying multi-bit flip-flops at the post-placement stage, which can be seamlessly integrated in modern design flow; 2) a new problem formulation for post-placement optimization with multi-bit flip-flops; 3) flip-flop clustering and placement algorithms to simultaneously minimize flip-flop power consumption and interconnecting wirelength; and 4) a progressive window-based optimization technique to reduce placement deviation and improve runtime efficiency of our algorithms. Experimental results show that our algorithms are very effective in reducing not only flip-flop power consumption but also clock tree and signal net wirelength. Consequently, the power consumption of the clock network is minimized.

With the thermal effect, improper analog placements may degrade circuit performance because the thermal impact from power devices can affect electrical characteristics of the thermally-sensitive devices. There is not much previous work that considers the desired placement configuration between power and thermally-sensitive devices for a better thermal profile to reduce the thermally-induced mismatches. This paper first introduces the properties of a desired thermal profile for better thermal matching of the matched devices. It then presents a thermal-driven analog placement methodology to achieve the desired thermal profile and to consider the best device matching under the thermal profile while satisfying the symmetry and the common-centroid constraints. Experimental results based on real analog circuits show that the proposed approach can achieve the best analog circuit performance/accuracy with the least impact due to the thermal gradient, among existing works.

Optimization for power is always one of the most important design objectives in modern nanometer IC design. Recent studies have shown the effectiveness of applying multi-bit flip-flops to save the power consumption of the clock network. However, all the previous works applied multi-bit flip-flops at earlier design stages, which could be very difficult to carry out the trade-off among power, timing, and other design objectives. This paper presents a novel power optimization method by incrementally applying more multi-bit flip-flops at the post-placement stage to gain more clock power saving while considering the placement density and timing slack constraints, and simultaneously minimizing interconnecting wirelength. Experimental results based on the industry benchmark circuits show that our approach is very effective and efficient, which can be seamlessly integrated in modern design flow.

With the thermal effect, improper analog placements may degrade circuit performance because the thermal impact from power devices can affect electrical characteristics of the thermally-sensitive devices. There is not much previous work that considers the desired placement configuration between power and thermally-sensitive devices for a better thermal profile to reduce the thermally-induced mismatches. In this paper, we first introduce the properties of a desired thermal profile for better thermal matching of the matched devices. We then propose a thermal-driven analog placement methodology to achieve the desired thermal profile and to consider the best device matching under the thermal profile while satisfying the symmetry and the common-centroid constraints. Experimental results based on real analog circuits show that our approach can achieve the best analog circuit performance/accuracy with the least impact due to the thermal gradient, among existing works.

To reduce the effect of parasitic mismatches and circuit sensitivity to thermal gradients or process variations for analog circuits, some pairs of modules need to be placed symmetrically with respect to a common axis, and the symmetric modules are preferred to be placed at closest proximity for better electrical properties. Most previous works handle the problem with symmetry constraints by imposing symmetric-feasible conditions in floorplan representations and using cost functions to minimize the distance between symmetric modules. Such approaches are inefficient due to the large search space and cannot guarantee the closest proximity of symmetry modules. In this paper, we present the first linear-time-packing algorithm for the placement with symmetry constraints using the topological floorplan representations. We first introduce the concept of a symmetry island which is formed by modules of the same symmetry group in a single connected placement. Based on this concept and the B*-tree representation, we propose automatically symmetric-feasible (ASF) B*-trees to directly model the placement of a symmetry island. We then present hierarchical B*-trees (HB*-trees) which can simultaneously optimize the placement with both symmetry islands and nonsymmetric modules. Unlike the previous works, our approach can place the symmetry modules in a symmetry group in close proximity and significantly reduce the search space based on the symmetry-island formulation. In particular, the packing time for an ASF-B*-tree or an HB*-tree is the same as that for a plain B*-tree (only linear) and much faster than previous works. Experimental results show that our approach achieves the best-published quality and runtime efficiency for analog placement.

In analog layout design, it is very important to reduce the parasitic coupling effects and improve the circuit performance. Consequently, the most important device-level placement constraints are matching, symmetry, and proximity. However, many previous works deal with these constraints separately, and none of them mention how to handle different constraints simultaneously and hierarchically. In this paper, we first give a case study to show the needs of integrating these constraints in a hierarchical manner. Then, we present the first formulation for analog placement based on hierarchical module clustering. Our approach can handle analog placement with various constraint groups including matching, (hierarchical) symmetry, and (hierarchical) proximity groups. To our best knowledge, this is also the first work in the literature to handle floorplanning with the clustering constraint using the B*-tree based representation. Experimental results based on industrial analog designs show that our approach is very effective and efficient.

In this paper, we present the first amortized linear-time packing algorithm for the placement with symmetry con-straints. We first introduce the concept of a symmetry is-land which is formed by modules of the same symmetry group in a single connected placement. Based on this con-cept and the B*-tree representation, we propose automati-cally symmetric-feasible B*-trees (ASF-B*-trees) to directly model the placement of a symmetry island. Unlike the pre-vious works that can handle only 1D symmetry constraints, our ASF-B*-tree is the first in the literature to addition-ally consider 2D symmetry. We then present hierarchical B*-trees (HB*-trees) which can simultaneously optimize the placement with both symmetry islands and non-symmetry modules. Unlike the previous works, our approach can guar-antee the close proximity of symmetry modules and signifi-cantly reduce the search space based on the symmetry-island formulation. In particular, the packing time for an ASF-B*-tree or an HB*-tree is the same as that for a plain B*-tree (only amortized linear) and much faster than previous works which need at least loglinear time. Experimental results show that our approach achieves the best published quality and runtime efficiency for analog placement.