In 3-D stacked integrated circuit (IC) manufacturing, for the acceptable high yield, it is essential to stack only known good dies by testing the individual dies at the prebond stage. While the postbonded 3-D IC is operated by a low power 3-D clock tree, the prebond testing requires a 2-D clock tree on each die. The previous work provided a prebond testable 3-D clock tree synthesis solution by allocating through-silicon via (TSV) buffers and redundant trees with transmission gates. However, no optimizations on the allocation and design of the resources have been addressed. In this paper, we propose practically viable clock tree optimization techniques under prebond testability: 1) TSV-buffer-aware topology generation techniques that enable an economical buffer allocation by preventing (potentially “bad”) TSV buffers; 2) delay-locked loop (DLL)-based 2-D clock network design method that offers a diverse exploration of 2-D clock tree synthesis and resource allocation for prebond die testing; and 3) a new circuit design technique of transmission gates that completely removes its control line. Compared to the existing topology generation algorithms, our proposed TSV-buffer-aware topology generation uses 68%-88% fewer TSVs, 36%-58% less wire resource, and 35%-69% fewer buffers while consuming 17%-43% less clock power for the benchmark circuits, and our proposed method of clock tree exploration provides many alternative structures of a 2-D clock tree, considering the resource balance between DLLs and wires. In addition, the use of our self-controlled clock transmission gate enables a drastic reduction of the total wirelength, which amounts to 18% on average.

For the cost-effective implementation of clock trees in through-silicon via (TSV)-based 3D IC designs, we propose core algorithms for 3D clock tree synthesis. For a given abstract tree topology, we propose DLE-3D ( d eferred l ayer e mbedding for 3D ICs), which optimally finds the embedding layers of tree nodes, so that the TSV cost required for a tree topology is minimized, and DME-3D ( d eferred m erge e mbedding for 3D ICs), which is an extended algorithm of the 2D merging segment, to minimize the total wirelength in 3D design space, with the consideration of the TSV effect on delay. In addition, when an abstract tree topology is not given, we propose NN-3D ( n earest n eighbor selection for 3D ICs), which constructs a (TSV and wirelength) cost-effective abstract tree topology for 3D ICs. Through experimentation, we have confirmed that the clock tree synthesis flow using the proposed algorithms is very effective, outperforming the existing 3D clock tree synthesis in terms of the number of TSVs, total wirelength, and clock power consumption.

This paper addresses a fundamental problem of zero skew clock tree embedding problem in 3D ICs. We propose an algorithm, called ZCTE-3D, for solving the zero skew clock tree embedding problem in 3D ICs for a given tree topology. The primary objective is to minimize the cost of TSVs together with finding embedding layers and the secondary objective is to minimize the cost of wirelength. We show that ZCTE-3D solves the problem optimally in polynomial time under the linear delay model, while it solves the problem suboptimally under the Elmore delay model. We also propose an effective 3D clock tree synthesis flow by integrating a multi-layer tree topology generation algorithm, called MMM-3D, into ZCTE-3D. Through an extensive exploitation of ZCTE-3D in experiments, we have analyzed the relation between the number of TSVs, the total wirelength, and tree topology. When compared with the results produced by the previous 3D clock tree synthesis algorithm BURITO, experimental results show that ZCTE-3D uses on average 10% less number of TSVs with similar wirelength and delay for the same tree topologies. Furthermore, by generating tree topologies with MMM-3D, we are able to reduce the number of TSVs by 10% on average even with 4% shorter wirelength and 2% reduced delay.

This paper proposes comprehensive solutions to the clock tree synthesis problem that provides pre-bond testability for 3D IC designs. In 3D ICs, it is essential to stack only good dies by testing the individual dies before stacking. For the clock signaling, the pre-bond testing requires a complete 2D clock tree on each die. The previous work enables the prebond testability by allocating specially designed resources called TSV-buffers and redundant trees with transmission gates. We proposes viable solutions to the two fundamental problems of the previous work: (1) using much less buffer resources by preventing (potentially 'bad') TSV-buffers with a new tree topology generation algorithm; (2) completely removing the transmission gate control lines by using a specially designed component called self controlled clock transmission gate (SCCTG). Compared to the existing 3D tree topology generation algorithms, solution 1 can use 56%--88% less number of TSVs, 53%--67% less number of buffers, 22%--65% less total wirelength, and 26%--43% less clock power for the benchmark circuits with dense sink placements. Moreover, solution 2 reduces the total wirelength of all the benchmark circuits by 17% and 23% on average for the 2-die and 4-die stacked 3D ICs, respectively.