This paper presents an integrated CMOS current driver designed for electrothermal micro-electromechanical-systems (MEMS) switches, fabricated using a 0.18$\mu $m Bipolar-CMOS-DMOS (BCD) process. Unlike conventional constant-voltage drivers typically employed for MEMS actuators with positive temperature coefficient of resistance (TCR), this driver adopts a constant-current actuation. This approach benefits series-connected array components, applications seeking enhanced electromigration control, as well as actuators exhibiting a negative TCR. The system includes a 6-bit programmable digital-to-analog converter, current multiplication circuits, and feedback diagnostic capabilities, enabling precise control and monitoring of actuator performance within a core area of 1.5 mm2. The driver supports pulse-width modulation (PWM) to significantly reduce power consumption compared to DC actuation and implements a double-pulse strategy for accelerating switch activation times. Diagnostic circuits measure actuator resistance within ± 0.5$\boldsymbol {\Omega }$and switching states to enhance reliability in safety-critical applications. Experimental validation confirmed that the driver successfully provides currents up to 110 mA with a resolution of 1.65 mA. At a minimum output voltage of 1.7 V, it can power electrothermal actuators with up to 775 mW under an 8 V supply voltage, corresponding to a power density of 517 mW/mm2. The driver was demonstrated to successfully actuate a chevron-style MEMS switch in 3.5 ms and maintain contact with a 76.7 mA, 50 % PWM waveform at 1 kHz, reducing power consumption by 30.72 %.

Previous efforts on reconfigurable analog circuits mostly focused on specialized analog circuits, produced through careful co-design, or on highly reconfigurable, but relatively resource inefficient, accelerators that implement analog compute paradigms. This work deals with an intermediate point in the design space: specialized reconfigurable circuits for analog compute paradigms. This class of circuits requires new methodologies for performing co-design, as prior techniques are typically highly specialized to conventional circuit classes (e.g., filters, ADCs). In this context, we present Ark, a programming language for describing analog compute paradigms. Ark enables progressive incorporation of analog behaviors into computations, and deploys a validator and dynamical system compiler for verifying and simulating computations. We use Ark to codify the design space for three different exemplary circuit design problems, and demonstrate that Ark helps exploring design trade-offs and evaluating the impact of non-idealities to the computation.

Main amplifiers are crucial components in the design of optical receivers, amplifying the output voltage of the transimpedance amplifier (TIA). While Cherry-Hooper (CH) amplifiers are widely utilized in optical receivers due to their high bandwidth, they often fall short in linearity, making them less suitable for PAM-4 and higher-order modulation schemes. This study presents a highly linear PAM-4 optical receiver design. The proposed main amplifier employs gm/gminverter-based amplifiers known for their superior linearity. We have applied the interleaving active feedback (IAFB) technique to enhance bandwidth while mitigating gain peaking. Notably, our proposed design operates with a 1 V supply, offers a bandwidth of 20 GHz at a gain of 64 V/V, and achieves a total harmonic distortion (THD) of less than 1% for a 600 mVppdifferential output swing.

A switched constant current driver for a configurable switch network based on electrothermal micro-electromechanical-systems (MEMS) components is presented. A constant current-mode approach is proposed for achieving precise power control over an array of devices that leverage thermal heaters for actuation. This multi-channel actuation circuit is able to power different electrothermal MEMS switches. Interface circuits based on the self-temperature sensing technique of the heater and the ohmic contact property of the actuator are proposed. They provide early detection to address MEMS lifetime concerns, and constitute the main novelty of this research, which is specifically focused on the application. The circuit is implemented in a 0.18 μm BCD technology and occupies an area of 1.3 mm2. Post-layout simulations show that the system can output current up to 90 mA (Rheater= 80 Ω) with a resolution of 2 mA.

This article presents a dual-bandwidth front-end (FE) for a rapidly reconfigurable dual data rate and power-proportional optical receiver. The proof-of-concept receiver FE is capable of operation at 8- and 4-Gb/s data rates. Implemented in 65-nm CMOS technology, the proposed FE consists of a shunt-feedback transimpedance amplifier (TIA), a configurable one-stage-to-three-stage postamplifier (PA), and an offset compensation (OC) loop. By reconfiguring the number of stages in the PA, the FE maintains a near-constant delay when its bandwidth is changed. This allows synchronization to be maintained, with limited bit errors when the target data rate is switched. The prototype receiver was measured with an optical input at 8 and 4 Gb/s. The overall FE dissipates 6.12 mW at 8 Gb/s (0.76 pJ/bit) and 2.86 mW at 4 Gb/s (0.72 pJ/bit). The measured receiver optical sensitivities for 8- and 4-Gb/s inputs at high-bandwidth (HBW) and low-bandwidth (LBW) modes are −7.7 and −9.8 dBm, respectively. The measurement results confirm the matched delay through the FE with delay variations within 8 ps.

This work presents simulation results of a single-ended source-series-terminated (SST) voltage-mode driver in 65 nm CMOS technology. The proposed driver operates in three different modes. The first mode uses symmetric feedforward equalization to drive a short electrical link, which introduces a total loss of 16 dB at 10 GHz including electrostatic discharge and wire bonding parasitics. The second mode drives a vertical cavity surface emitting laser (VCSEL) diode through an electrical link, employing asymmetric equalization to compensate for the VCSEL nonlinear behavior. The third mode directly drives the VCSEL diode also using asymmetric equalization. The proposed driver provides a tunable output swing without affecting the output impedance of the driver. Furthermore, the driver offers tunable output impedance based on the selected mode of operation. Through simulation, this triple-mode driver operates at up to 20 Gb/s and is estimated to dissipate a maximum power of 27.57 mW when driving a VCSEL through an electrical link.

In this work, a single-event transient tolerant optical receiver using triple modular redundancy (TMR) is presented. The TMR method splits a conventional receiver into three identical receivers in parallel. Majority voting is performed at the outputs after the received signal has been sliced. The proposed SET tolerant optical receiver achieves a gain of 83 dB$\Omega$, a bandwidth of 7.2 GHz, and an input-referred noise current of 0.93 $\mu \mathrm{A}_{rms}$. It operates at a supply voltage of 1 V and dissipates 33 mW of power. Analysis shows that adding TMR introduces a sensitivity penalty of only 0.8 dB.

Neuromorphic computing seeks to build hardware systems that are similar to the brain in form and function. Such systems are composed of artificial neurons and synapses, both of which will have to operate with extreme energy efficiency to allow spiking neural networks to scale to the size of the brain. In this work, we present such a low-power subthreshold implementation of the Izhikevich neuron model, inspired by the circuit introduced by Wijekoon and Dudek. The circuit, designed in the UMC 65nm process, consumes 11.74fJ/spike at a 0.18V supply voltage, while operating on a biological timescale and allowing analog tunability of control voltages so as to exhibit different spiking behaviors. The circuit comprises an integrated digital spike transceiver that communicates with AER arbitration circuitry and generates reset pulses.

A fast turn-on front-end (FE) for a burst-mode nonreturn to zero (NRZ) receiver targeting vertical cavity surface-emitting laser (VCSEL)-based optical links operating at 10 Gb/s/ch is presented. Its bandwidth and power are reconfigurable for energy-efficient burst-mode operation. The circuit design for 4.9 ns power-ON time using a power-gating approach is presented. Rapid power-ON is achieved using the regeneration of a high-speed latch, activated by a quarter-rate clock. Implemented in a 65-nm CMOS technology, the proposed FE consists of a shunt-feedback transimpedance amplifier (TIA), a configurable one-stage or four-stage postamplifier (PA) and an offset compensation loop. By reconfiguring the number of stages in the PA from four to one, power dissipation, and the FE bandwidth are reduced during periods of link inactivity while still maintaining sufficient gain to allow the detection of an incoming burst. The presented work is supported by simulation and measurement results with optical inputs at 10 Gb/s. The results demonstrate a 4.9-ns turn-on time, corresponding to 49 unit intervals (UIs). The overall FE dissipates 5.7 mW at 10 Gb/s (0.57 pJ/bit) and 1.9 mW during idle periods. The complete receiver of each channel occupies an area of 95$\mu \text{m}\,\,\times81\,\,\mu \text{m}$. A 5% area overhead is introduced by the burst sensing circuit.

A selective harmonic elimination pulse width modulation (SHEPWM) class-D amplifier (CDA) with a reconfigurable gate driver integrated circuit (IC) is proposed. The H-bridge CDA generates a three-level SHEPWM signal and cancels lower order harmonics of the switching voltage. To generate accurate pulses at the right switching angles, GaN devices are used and a reconfigurable gate driver IC is used to control the driving strength of the gate driver. The SHEPWM algorithm is implemented in an FPGA and can configure the output on-the-fly. The simulation results show that the SHEPWM CDA has a 0.48 % total harmonic distortion (THD) for a 10 kHz output with an estimated switching loss of 38 mW for a GaN power transistor. It also shows that the driving strength of the gate driver has very little effect on THD, therefore the driving strength can be optimized between overshoot voltage and switching loss without concern for THD.

This paper presents a new dual-inductor hybrid boost converter (DI-HBOC) with two inductors located at the output. This structure allows continuous current delivered to the load, thus, reducing the output filtering capacitor size and the output voltage ripple. By relocating the inductor at the output, which is the lower current path, the conduction loss on the inductor can be significantly reduced. The right half plane zero (RHPZ) in the control-to-output transfer function can also be eliminated; therefore, a simple pulse-width modulation (PWM) voltage-mode controller can be used for the proposed DI-HBOC while still achieving high closed-loop bandwidth and fast transient response. The distinct features of the proposed converter are analytically demonstrated. A 12-to 24 V DI-HBOC and a conventional BOC (CBOC) using low-ÆoN GaN switches with PWM voltage-mode controller are also implemented in PSIM for verification and comparison. The simulated peak power efficiency is 97.4 % that is 1.17 % higher than the CBOC. At 3 A load current, the power efficiency is improved by 9.7 % and the output ripple is only 17.5 mV, 6x lower than in CBOC.

This paper presents a novel and compact bandgap comparator (BGRCOMP) for under-voltage lockout (UVLO) and thermal shutdown (TSD) protection circuits. The proposed BGRCOMP is self-referenced and combines the advantages of both a high-accuracy bandgap reference and a comparator into one single circuit. A latch-controlled biasing technique is also presented, which reduces static power consumption of the proposed BGRCOMP. The proposed BGRCOMP is used for the design of compact and low power UVLO and TSD circuits. The post-layout simulation results using a 0.18 μm BCD-on-SOI technology prove the attractive performance of the UVLO and TSD with a static current (Iq) of 7.76 μA and 5.4 μA from a 5 V supply, respectively. The deviations of UVLO thresholds are less than 3 mV in the temperature range of -40~85 °C.

This paper presents a source-synchronous receiver architecture for use in parallel optical links. The proposed system is reconfigurable, allowing any channel to be used as a clock or data lane. The architecture is designed for modedivision multiplexed (MDM) optical links with forwarded clocks and allows the sensitive clock signal to be placed in the lane with the least amount of optical crosstalk for a given photonic interconnect. This configurability, which accounts for variation in integrated optics by leveraging the more robust electronic chip, optimizes the performance in electronic/optic codesigned solutions and may improve the yield. The architecture contains a dynamic clock distribution network, able to send a reference clock signal from the chosen clock receiver to any other data-configured receiver. The proposed architecture has been implemented on an experimental chip consisting of two receivers designed in the 65-nm CMOS technology. Electrical measurements at 8 Gb/s were done, and bit error rate curves are presented. They demonstrate the ability to swap and repurpose the clock and data inputs between the receivers, with similar sensitivity upon reconfiguration as a proof of concept.

Optical receiver front ends that are intentionally designed to have a bandwidth low enough that significant intersymbol interference (ISI) is introduced are becoming commonplace. Although the resultant ISI must be removed using an equalizer, the lower bandwidth allows for higher gain in the front-end's first stage, lower input-referred noise, and fewer gain stages. With fewer main-amplifier stages, power dissipation is reduced. The noise analysis of these front ends presents several challenges. This paper derives integrated input-referred noise for inverter-based shunt-feedback transimpedance amplifiers from first principles and highlights the importance of correctly estimating the gain and noise bandwidth of the receiver. The notion of the effective gain of the receiver is introduced, which is lower than the midband gain typically used in noise calculations. The analysis of the inverter-based TIA is used to discuss the important design trade-offs depending on the type of equalizer used. Integrated input-referred noise is derived and compared for front-ends using decision-feedback equalizers (DFEs), continuous-time linear equalizers, and feed-forward equalizers. The simulation results show that a DFE-based receiver achieves the lowest input-referred noise.

This paper presents a design technique for optical receivers that adjusts the damping factor of a 2nd-order transimpedance amplifier (TIA) synchronously with the incoming data. This approach allows the fast response of low-damping factor while mitigating the intersymbol interference (ISI) associated with underdamped systems. A differential shunt-feedback TIA (SF-TIA) is optimized to reach its minimum input-referred noise, with and without cross-coupled inverters at its output. The negative transconductance introduced at the TIA's output improves bandwidth, noise performance and vertical eye opening (VEO). Dynamic damping is introduced by adding a triode-region transistor with a time-varying bias voltage across the outputs which modulates the damping factor of the system from -0.42 to 3.5 each unit interval. With dynamic damping, the TIA achieves more than twice the VEO compared to the optimized reference TIA.

This paper presents a source-synchronous receiver architecture for use in parallel optical links. The proposed system is reconfigurable, allowing any channel to be used as a clock or data lane. The architecture is designed for mode-division multiplexed (MDM) optical links with forwarded clocks and allows the sensitive clock signal to be placed in the lane with the least amount of optical crosstalk for a given photonic interconnect. This configurability, which accounts for variation in integrated optics by leveraging the more robust electronic chip, optimizes the performance in electronic/optic codesigned solutions and may improve the yield. The architecture contains a dynamic clock distribution network, able to send a reference clock signal from the chosen clock receiver to any other data-configured receiver. The proposed architecture has been implemented on an experimental chip consisting of two receivers designed in the 65-nm CMOS technology. Electrical measurements at 8 Gb/s were done, and bit error rate curves are presented. They demonstrate the ability to swap and repurpose the clock and data inputs between the receivers, with similar sensitivity upon reconfiguration as a proof of concept.

This paper presents a transceiver for a long on-chip link in 130-nm CMOS. It features a hybrid-mode transmitter with a current sense amplifier receiver. From the perspective of power efficiency, voltage-mode pre-emphasis is preferred because it reduces the current consumption of the circuit. Based on simulations, an on-chip link in 130-nm CMOS achieves 8 Gb/s over 5-mm long interconnects, while consuming 256 fJ/bit corresponding to 51.2 fJ/bit/mm with 1.2 V supply.

This paper presents the mixed-signal circuit implementation of reduced complexity algorithms for decoding low-density parity check (LDPC) codes. Based on modified differential decoding using binary message passing (MDD-BMP), binary addition using discrete-time digital circuits is replaced by continuous-time analog-current summation. Potential degradation due to the mismatch between current sources, P/N strength mismatch and inverter-threshold mismatch is considered in behavioural simulation and shown to be tolerable. Area estimates suggest a reduction from 0.27 mm2to 0.11 mm2for the FG(273, 191) code. Finally, transistor level simulation of the FG(273, 191) code using TSMC 65 nm technology shows an efficiency of 0.56 pJ/bit.

A voltage-controlled oscillator linearization technique suitable for dual-path phase-locked loops is presented. In the proposed scheme, the state of the integral control path sets the gain of a transconductor in the proportional path in such way that nearly constant VCO gain through the proportional path is achieved. A detailed analysis and design example is presented in the context of delay-interpolating ring-based VCOs. Simulation and measurements in ST 90 nm CMOS technology show that the proposed technique is effective in reducing gain variations across the VCO's tuning range from an uncompensated spread of 1:4 to an average of 1:1.3.

In traditional phase-locked loop (PLL) designs, the loop bandwidth is limited to ~1/10thof the frequency of the reference clock due to the discrete-time nature of the system. The loop bandwidth also sets the frequency above which no significant suppression of the phase noise of the oscillator in the PLL occurs. This paper describes a PLL architecture in which the output of an additional charge pump drives a feed-forward path that extends outside of the PLL's feedback loop. This path drives a phase interpolator, allowing for phase-error correction to occur beyond the bandwidth of the PLL. The proposed architecture is investigated through linear analysis. Measurements of a test chip designed in TSMC 90 nm technology show that the proposed architecture is effective in reducing PLL phase noise.

This work presents the design and performance of an inductorless, power proportional tunable optical receiver front-end in TSMC 90nm CMOS technology. The proposed optical receiver front-end includes a transimpedance amplifier (TIA) and a post amplifier. The TIA uses the shunt feedback topology with a current controlling a MOSFET array, and the post amplifier uses a common source topology loaded with active inductors. The receiver front-end has the ability to tune from 1.25 Gb/s data rate to 15 Gb/s with proportional power dissipation and a constant gain of 84 dBΩ. The overall power dissipation varies from 0.94 mW to 7.46 mW as the data rate scales maintaining power dissipation below 800 fJ/bit at all data rates. The variable 3 dB bandwidth is from 886.1 MHz to 10.83 GHz with an input referred noise density from 4.307 pA/sqrt(Hz) to 14.27 pA/sqrt(Hz).

In this work we propose a mismatch-robust VCO frequency comparison circuit based on the absolute period-measurement of the two frequencies. The main idea of the work is to increase the overall calibration precision by employing a multiplexer in the input, thereby allowing both signals to use the same path including a single Time-to-Voltage Converter circuit (TVC). Ultimately, this would result in lower overall mismatch and better accuracy compared to the case where the current sources of the two different TVCs must be carefully matched. The simulated frequency error is found to be less than 0.8% after only 4 reference cycles. The proposed scheme is also simulated against Process, Voltage, and Temperature (PVT) variations.

Wake-up receivers (WuRx) have been recently employed in ultra-low power transceivers as a power efficient approach. In this work, we combine the idea of subsampling and the uncertain-IF structure in order to design and implement an ultralow-power WuRx for 915MHz ISM band applications. Based on extracted post-layout simulation results, the proposed WuRx draws 56μA from a 0.5-V supply and has a sensitivity of -70dBm. The new WuRx occupies an area of 0.15 mm2(including the pads) in TSMC90nm CMOS technology.

In this paper we introduce a new flip-flop for use in a low- swing LC resonant clocking scheme. The proposed low-swing differential conditional capturing flip-flop (LS-DCCFF) operates with a low-swing sinusoidal clock through the utilization of reduced swing inverters at the clock port. The functionality of the proposed flip-flop was verified at extreme corners through simulations with parasitics extracted from layout. The LS-DCCFF enables 6.5% reduction in power compared to the full- swing flip-flop with 19% area overhead. In addition, a frequency dependent delay associated with driving pulsed flip-flops with a low-swing sinusoidal clock has been characterized. The LS-DCCFF has 870 ps longer data to output delay as compared to the full-swing flip-flop at the same setup time for a 100 MHz sinusoidal clock. The functionality of the proposed flip-flop was tested and verified by using the LS-DCCFF in a dual-mode multiply and accumulate (MAC) unit fabricated in TSMC 90-nm CMOS technology. Low-swing resonant clocking achieved around 5.8% reduction in total power with 5.7% area overhead for the MAC.

An inductive feedback approach for BW extension of transimpedance amplifiers has been proposed. The effect of parasitic capacitances of the MOS transistor has been reduced using this approach. The process of zero-pole cancellation to extend the BW of the amplifier has been explained. To demonstrate the feasibility of the technique a new transimpedance amplifier has been simulated in a well-known CMOS technology (i.e. 90 nm STMicroelectronics). It achieves a 3-dB bandwidth of more than 16GHz in the presence of a 150fF photodiode capacitance and 5fF loading capacitance while only dissipating 2.2 mW. Despite this low power dissipation, the amplifier shows superior noise performance.