This paper presents a detailed comparison between the two commonly used capacitive DAC architectures for 10-bit SAR ADCs: binary-weighted and split-capacitor DACs. These DAC architectures are compared based on the impact of unit-capacitor mismatch and parasitic capacitance on their linearity, area and power consumption. The split-capacitor DAC is shown to be much more sensitive to unit-capacitor mismatch and parasitic capacitances as opposed to the binary-weighted DACs. Unit-capacitor values are then calculated for the split-capacitor and binary-weighted DAC topologies under two orthogonal scenarios: (a) Fixed linearity at the expense of the area and power consumption and (b) Maximizing the linearity within a specified area budget. In-spite of requiring significantly lower number of unit elements as compared to a binary-weighted DAC, split-capacitor DAC yields a larger value of unit-capacitor and total DAC capacitance for fixed linearity scenario and conversely results in a lower effective number of bits (ENOB) for a fixed area specification. Based on our analysis, binary DAC is found to be more area and power efficient than its split capacitor counterpart.

Filter-banks based on a gm-C topology are popular in acoustic sensor systems targeting spectral analysis. Their benefits lie in a very low power consumption and center-frequency scalability through gm-tuning to cover the audio frequency range. However the linear signal swing at the output of the filter is limited due to the inherent non-linearity of the input transistors in a differential pair. This work assesses the impact of noise and center-frequency specifications on the power consumption of 2 OTA base gm-C bandpass filters, both from a theoretical and practical point of view. Next, we introduce a novel scalable switched-capacitor based degeneration technique that enhances the linear signal swing at the filter output. Simulation results in 90nm CMOS demonstrate a power consumption of only 44nW for a bandpass filter with Q-factor of 1 with 63 dB dynamic range (<; 2% THD) and a center-frequency of 100Hz. This scales to only 1.4 μW for a center-frequency at 3.2kHz. These power consumption numbers compare favorably with the state-of-the-art and enhance the Figure of Merit by more than 1.5X for a similar dynamic range.

We derive a closed-form quasi-static model for the coupling impedance between aligned coplanar rectangular contacts on bulk and epitaxial semiconductor substrates by resolving the 3-D field lines into simpler components (vertical, lateral, fringing, 2-D, etc.). Both insulating and conducting (grounded or floating) backplane conditions are considered. Our model reflects all the geometry and process parameters, and its constants are process independent and universal. The model also gives the capacitive coupling via ambient, i.e., via the region outside the substrate, and specifies conditions under which a given thickness or lateral extension of the substrate can be regarded as infinite. Comparisons with technology computer-aided design simulations and measurements validate the model over a wide range of width/length and width/separation ratios of the contacts.