This paper proposes a novel CT image coding concept named LOI which stands for level of interest and coding methods based on that concept. The well-known ROI (region of interest) coding gives priority to pixels in particular regions of an image when encoding or decoding the image. Similarly, LOI coding gives priority to the pixels having a particular pixel level. LOI is ideal for coding of CT images and offers remarkably high coding efficiency. This paper proposes two types of LOI coding methods. One type is the floating point method and the other is the integer method. This paper verifies that the both types improve coding efficiency of pixels in the LOI window. This paper also shows that adequate image quality is obtained even if the viewing window is different from the LOI window.

This paper proposes novel techniques for reducing tiling artifacts and encoding time which are two of the largest problems with the JPEG2000 encoder. The proposed method detects tiling artifacts during the coding process and reduces them automatically using tile-boundary adaptive post-quantization. It also provides a higher speed JPEG2000 coding process. This accelerated performance was obtained by predicting the truncation points using the entropy of wavelet transform coefficients prior to the arithmetic coding. This encoding method also requires no additional processing in the decoder. In the experiment, it was subjectively confirmed that tiling artifacts were greatly reduced and that the coding process was considerably accelerated.

This paper proposes the tile size conversion method for the wavelet image transcoding gateway and a set of methods to reduce the tile boundary artifacts caused by the conversion.In the wavelet image coding system represented by JPEG2000, pictures are usually divided into one or more tiles and each tile then transformed separately. On low memory terminals such as mobile terminals, some decoders are likely to have limits on what tile sizes they can decode. Assuming a system using these limited decoders, methods were investigated for converting the tile size quickly and automatically at the gateway when image data with a non-decodable tile size is received at the gateway from another system. Furthermore, tile boundary artifacts reduction methods are investigated. This paper proposes a basic method, which creates a tiled wavelet coefficient sequence from a non-tiled wavelet coefficient sequence. This paper also verifies the validity of the proposed scheme by implementing it with a 5x3 reversible filter and a 9x7 irreversible filter.

This paper investigates substrate noise influence on circuit performance in a variable threshold-voltage scheme (VT scheme) where threshold voltage is dynamically varied by substrate-bias control to reduce active power dissipation. It is experimentally examined that substrate-bias can be controlled stably with very few substrate-contacts. Measured tracking jitter of a delay-locked loop implemented by interconnections in an 8 mm-square gate array does not degrade even when substrate-contacts are removed except for one at every strip of p-sub and n-well: A 2 mm-square discrete cosine transform core processor with no substrate-contact except in its periphery operates at supply voltages from 1.3 V to above 3 V even though it employs small-swing differential dynamic pass-transistor logic. No performance degradation nor latchup is observed in these chips even when 100 k/spl Omega/ resistance is added to the substrate. These experimental results demonstrate noise immunity of the VT scheme, and indicate the possibility that the VT scheme can be applied to existing macro design easily.