In the resource allocation problem (RAP), the goal is to divide a given amount of a resource over a set of activities while minimizing the cost of this allocation and possibly satisfying constraints on allocations to subsets of the activities. Most solution approaches for the RAP and its extensions allow each activity to have its own cost function. However, in many applications, often the structure of the objective function is the same for each activity, and the difference between the cost functions lies in different parameter choices, such as, for example, the multiplicative factors. In this article, we introduce a new class of objective functions that captures a significant number of the objectives occurring in studied applications. These objectives are characterized by a shared structure of the cost function depending on two input parameters. We show that, given the two input parameters, there exists a solution to the RAP that is optimal for any choice of the shared structure. As a consequence, this problem reduces to the quadratic RAP, making available the vast amount of solution approaches and algorithms for the latter problem. We show the impact of our reduction result on several applications, and in particular, we improve the best-known worst-case complexity bound of two problems in vessel routing and processor scheduling from [Formula: see text] to [Formula: see text]. Summary of Contribution: The resource allocation problem (RAP) with submodular constraints and its special cases are classic problems in operations research. Because these problems are studied in many different scientific disciplines, many conceptual insights, structural properties, and solution approaches have been reinvented and rediscovered many times. The goal of this article is to reduce the amount of future reinventions and rediscoveries by bringing together these different perspectives on RAPs in a way that is accessible to researchers with different backgrounds. The article serves as an exposition on RAPs and on their wide applicability in many areas, including telecommunications, energy, and logistics. In particular, we provide tools and examples that can be used to formulate and solve problems in these areas as RAPs. To accomplish this, we make three concrete contributions. First, we provide a survey on algorithms and complexity results for RAPs and discuss several recent advances in these areas. Second, we show that many objectives for RAPs can be reduced to a (simpler) quadratic objective function, which makes available the extensive collection of fast and efficient algorithms for quadratic RAPs to solve these problems. Third, we discuss the impact that RAPs and the aforementioned reduction result can make in several application areas.

For a graph G=(V(G),E(G)), an Italian dominating function (ID function) of G is a function f:V(G)→{0,1,2} such that for each vertex v∈V(G) with f(v)=0, f(N(v))≥2, that is, either there is a vertex u∈N(v) with f(u)=2 or there are two vertices x,y∈N(v) with f(x)=f(y)=1. A function f:V(G)→{0,1,2} is a covering Italian dominating function (CID function) of G if f is an ID function and {v∈V(G)∣f(v)≠0} is a vertex cover set. The covering Italian domination number (CID number) γcI(G) is the minimum weight taken over all CID functions of G.In this paper, we study the CID number in graphs. We show that the problem of computing this parameter is NP-hard even when restricted to some well-known families of graphs, and find some bounds on this parameter. We characterize the family of graphs for which their CID numbers attain the upper bound twice their vertex cover number as well as all claw-free graphs whose CID numbers attain the lower bound half of their orders. We also give the characterizations of some families of graphs with small CID numbers.

Many multicore processors are capable of decreasing the voltage and clock frequency to save energy at the cost of an increased delay. While a large part of the theory oriented literature focuses on local dynamic voltage and frequency scaling (local DVFS), where every core's voltage and clock frequency can be set separately, this article presents an in-depth theoretical study of the more commonly available global DVFS that makes such changes for the entire chip. This article shows how to choose the optimal clock frequencies that minimize the energy for global DVFS, and it discusses the relationship between scheduling and optimal global DVFS. Formulas are given to find this optimum under time constraints, including proofs thereof. The problem of simultaneously choosing clock frequencies and a schedule that together minimize the energy consumption is discussed, and based on this a scheduling criterion is derived that implicitly assigns frequencies and minimizes energy consumption. Furthermore, this article studies the effectivity of a large class of scheduling algorithms with regard to the derived criterion, and a bound on the maximal relative deviation is given. Simulations show that with our techniques an energy reduction of 30% can be achieved with respect to state-of-the-art research.

Computers can reduce their power consumption by decreasing their speed using Dynamic Voltage and Frequency Scaling (DVFS). A form of DVFS for multicore processors is global DVFS, where the voltage and clock frequency is shared among all processor cores. Because global DVFS is efficient and cheap to implement, it is used in modern multicore processors like the IBM Power 7, ARM Cortex A9 and NVIDIA Tegra 2. This theory oriented paper discusses energy optimal DVFS algorithms for such processors. There are no known provably optimal algorithms that minimize the energy consumption of nontrivial real-time applications on a global DVFS system. Such algorithms only exist for single core systems, or for simpler application models. While many DVFS algorithms focus on tasks, this theoretical study is conceptually different and focuses on the amount of parallelism. We provide a transformation from a multicore problem to a single core problem, by using the amount of parallelism of an application. Then existing single core algorithms can be used to find the optimal solution. Furthermore, we extend an existing single core algorithm such that it takes static power into account.

Integrated circuits are tested thoroughly in order to meet the high demands on quality. As an additional step, outlier detection is used to detect potential unreliable chips such that quality can be improved further. However, it is often unclear to which tests outlier detection should be applied and how the parameters must be set, such that outliers are detected and yield loss remains limited. In this paper we introduce a mathematical framework, that given a set of target devices, can select tests for outlier detection and set the parameters for each outlier detection method. We provide results on real world data and analyze the resulting yield loss and missed targets.

We present an online outlier detection method that is applicable to Final Test. Test limits are constructed based on previous measurements and robust statistics are used to ensure a stable start to the method. We analyze our method using real-world data. Furthermore, we identified some cases which can result in performance degradation, but most experiments show that our method is robust to outliers and able to detect them in an online setting.

Design-time application mapping is limited to a predefined set of applications and a static platform. Resource management at run-time is required to handle future changes in the application set, and to provide some degree of fault tolerance, due to imperfect production processes and wear of materials. This paper concerns resource allocation at run-time, allowing multiple real-time applications to run simultaneously on a heterogeneous MPSoC. Low-complexity algorithms are required, in order to respond fast enough to unpredictable execution requests. We present a decomposition of this problem into four phases. The allocation of tasks to specific locations in the platform is the main contribution of this work. Experiments on a real platform show the feasibility of this approach, with execution times in tens of milliseconds for a single allocation attempt.

In this paper, we present an algorithm for run-time allocation of hardware resources to software applications. We define the sub-problem of run-time spatial mapping and demonstrate our concept for streaming applications on heterogeneous MPSoCs. The underlying algorithm and the methods used therein are implemented and their use is demonstrated with an illustrative example.

We propose a general clustering algorithm for dynamic sensor networks, that makes localized decisions (1-hop neighbourhood) and produces disjoint clusters. The purpose is to extract and emphasise the essential clustering mechanisms common for a set of state-of-the-art algorithms, which allows for a better understanding of these algorithms and facilitates the definition and demonstration of common properties.

Wireless networks are created by the communication links between a collection of radio transceivers. The nature of wireless transmissions does not lead to arbitrary undirected graphs but to structured graphs which we characterize by the polynomially bounded growth property. In contrast to many existing graph models for wireless networks, the property of polynomially bounded growth is defined independently of geometric data such as positional information. On such wireless networks, we present an approach that can be used to create polynomial-time approximation schemes for several optimization problems called the local neighborhood-based scheme. We apply this approach to the problems of seeking maximum (weight) independent sets and minimum dominating sets. These are two important problems in the area of wireless communication networks and are also used in many applications ranging from clustering to routing strategies. However, the approach is presented in a general fashion since it can be applied to other problems as well. The approach for the approximation schemes is robust in the sense that it accepts any undirected graph as input and either outputs a solution of desired quality or correctly asserts that the graph presented as input does not satisfy the structural assumption of a wireless network (an NP-hard problem).

This work evaluates an algorithm that maps a number of communicating processes to a heterogeneous tiled system on chip (SoC) architecture at run-time. The mapping algorithm minimizes the total amount of energy consumption, while still providing an adequate quality of service (QoS). A realistic example is mapped using this algorithm.