A novel fault tolerant methodology known as Codeword Prediction Encoder (CPE) for reliable data transmission using unreliable hardware is proposed. Simulation results show that performance of CPE is much better as compared to transmitting data by employing traditional encoding methodology. It is shown that by employing Min-sum decoding mechanisms and a strong encoder r = 1/2 and dv = 4, it is possible to correct all errors given that gate errors smaller than Pg = 6e-4. In general, CPE performance improvement of upto 10K is observed when compared to the normal encoding mechanism.

Traditional logic synthesis methodologies are driven by timing, power, and area constraints. However, due to aggressive technology shrinking and lower power requirements, circuit reliability is fast turning out to be yet another major constraint in the VLSI design flow. Soft errors, which traditionally affected only the memories, are now also resulting in logic circuit reliability degradation. In this paper, we present a systematic and integrated methodology to address and improve the combinational circuit reliability measured in terms of Soft Error Rate (SER). The proposed SER reduction framework makes use of rewriting based logic optimisation technique which employs local transformations. The main idea behind our proposal is to replace parts of the circuit with functionally equivalent but more reliable counterparts chosen from a pre-computed subset of Negation-Permutation-Negation (NPN) classes of 4-variable functions. Cut enumeration and Boolean matching driven by reliability aware optimisation algorithm are used to identify best possible replacement candidates. Our experiments on a set of MCNC benchmark circuits indicate that the proposed framework can achieve up to 75% reduction of output error probability. On average, about 14% SER reduction is obtained at the expense of very low area overhead of 6.57% that results in 13.52% higher power consumption.

In this paper, several implementations of the recently introduced PGDBF decoder for LDPC codes are proposed. In [2], the authors show that using randomness in bit-flipping decoders can greatly improve the error correction performance. In this paper, two models of random generators are proposed and compared through hardware implementation and performance simulation. A conventional implementation of the random generator through LFSR as a first design, and a new approach using binary sequences that are produced by the LDPC decoder, named IVRG, as second design. We show that both implementation of the PGDBF improve greatly the error correction performance, while maintaining the same large throughtput. However, the performance gain requires a large hardware overhead in the case of LFSR-PGDBF, while the overhead is limited to only 10% in the case of the IVRG-PGDBF.

In communication systems, channel quality variation is a well known phenomenon, which fundamentally influences the decoding process. While most of the time, the transmission takes place in good signal to noise conditions, to satisfy QoS requirements in all cases, telecom platforms rely on largely over-designed hardware, which may result in energy waste during most of their operation. In this paper we propose to exploit the channel noise variability and adapt the platform operation conditions such that QoS requirements are satisfied with the minimum energy consumption. In particular, we propose a technique to exploit channel noise variability towards energy effective LDPC decoding amenable to low-energy operation. Endowed with the channel noise variability knowledge, our technique adaptively tunes the operating voltage at runtime, aiming to achieve the optimal tradeoff between decoder performance and power con-sumption, while fulfilling the QoS requirements. To demonstrate the capabilities of our proposal we implemented it and other state of the art energy reduction methods in conjunction with a fully parallel LDPC decoder on a Virtex-6 FPGA. Our experiments indicate that the proposed technique outperforms state of the art counterparts, in terms of energy reduction, with 71% to 76% and 15% to 28%, w.r.t. early termination without and with DVS, respectively, while maintaining the targeted decoding robustness. Moreover, the measurements suggest that in certain conditions Degradation Stochastic Resonance occurs, i.e., the energy consumption is unexpectedly diminished due to the fact that unpredictable underpowered components facilitate rather than impede the decoding process.

Nowadays, the technology advancements of sensors, low power mixed-signal/RF circuits, wireless communication and Wireless Sensor Networks (WSNs) have enabled the design of compact, low power, high performance and low cost solutions for a wide range of applications, surveillance, building monitoring, sports/fitness, and of particular interesting are applications for health care. Novel sensors for human biomedical signal together with wireless connectivity and low power solutions are creating new opportunities for wearable devices which allow continuous monitoring together with freedom of movement of the users. This paper presents a low-power wearable sensor networks platform for on-body physiological measurements and wireless data communications. The platform hosts novel high sensitivity electric potential dry surface sensors that can be used in either contact or non-contact mode to measure ECG and EMG signals. Heart rate and respiration rate is performed runtime directly on the node. This approach reduces the amount of data than need to be transmitted, from raw measurement to analyzed data. In doing so the duty cycle of the radio has been reduced and the power consumption of the node optimized. Experimental measurements show the acquisition and processing of data from sensors and the low power consumption achieved with the node in different modalities.

Low Density Parity Check (LDPC) codes over GF(2m,)are an extension of binary LDPC codes. Performances of GF(2m,) LDPC codes have been shown to be higher than binary LDPC codes, but the complexity of the encoders/decoders increases. Hence there is a substantial lack of implementations for LDPC codes over GF(2m,)codes. This paper presents a class of quasi-cyclic LDPC codes over GF(2m,). These codes can alleviate the encoding/decoding complexity without excessive loss of performances. It is shown how, from a performance point of view, such codes are better than m times bigger binary codes and as good as (2m,)longer binary codes.

This paper presents an energy-efficient medium access control protocol suitable for communication in a wireless body area network for remote monitoring of physiological signals such as EEG and ECG. The protocol takes advantage of the static nature of the body area network to implement the effective time-division multiple access (TDMA) strategy with very little amount of overhead and almost no idle listening (by static, we refer to the fixed topology of the network investigated). The main goal is to develop energy-efficient and reliable communication protocol to support streaming of large amount of data. TDMA synchronization problems are discussed and solutions are presented. Equations for duty cycle calculation are also derived for power consumption and battery life predictions. The power consumption model was also validated through measurements. Our results show that the protocol is energy efficient for streaming communication as well as sending short bursts of data, and thus can be used for different types of physiological signals with different sample rates. The protocol is implemented on the analog devices ADF7020 RF transceivers.