The time division multiplexing technique overcomes the bandwidth limitation by allowing FPGA chips to transmit multiple signals the maximum clocking frequency. With the additional multiplexers, this technique dramatically increases system-level routing capability in the FPGA-based emulator. However, the large number of virtual wires in the chip interconnection may impact emulation performance. The system-level FPGA routing tends to connect all virtual wires (signals) and considers emulation performance. At the same time, the challenge for system-level FPGA routing using time division multiplexing lies in the emulation performance.

2-D directed self-assembly (DSA) is an emerging lithography for the 5-nm process node and beyond that can substantially increase design flexibility in critical routing layers and reduce the number of cuts for better yield. The state-of-the-art 2-D DSA process manipulates the orientation of double posts inside guiding templates to guide block copolymers (BCPs) to form 2-D patterns. However, a key challenge arises on how to correctly assign double post orientations and place cut patterns to make desired net connections for a given routing instance. In this paper, we propose a novel 2-D DSA-compliant routing (2-D-DCR) framework to systematically derive feasible orientation assignments for double posts to maximize routability. Specifically, 2-D-DCR features a complete set of new routing rules which transform the underlying physical BCP growth principles for large-scale routing, adopts a network-flow-based double-post assignment routing algorithm, and leverages a 2-D DSA line-end creation property to maximally reduce line-end cuts. Experimental results show that our 2-D-DCR can effectively generate a 2-D-DCR solution with zero double post conflicts, maximized routability, and minimized the number of cuts.

Along with the progress in automation and Industry 4.0, the use of industrial robots becomes much more popular. Meanwhile, the conventional manipulative devices, such as teaching pendant and joystick, are not intuitive enough and very time-consuming for task teaching. In facing more complicated tasks these days, it then induces high cost and demands experts with proper training. This paper thus aims to develop an intuitive manipulatory interface for assistance in simplifying the teaching process. We propose a wireless 3D manipulation system based on augmented reality (AR) with the tablet PC as the platform. The system allows the user to govern the movement of the real robot in a 3D space via a virtual one generated through the AR. We also develop several intelligent tools to assist the manipulation, so that accurate and collision-free path can be generated for the robot to follow for task execution. In addition, the system can also be used for offline training, which yields salient training effect for the operator. Experiments are executed to demonstrate the effectiveness of the proposed system, and questionnaires conducted to investigate user's response.

1-D nanowires are one of the most promising next-generation lithography technologies for 7 nm process node and beyond. The 1-D nanowire process first constructs a 1-D nanoarray through template synthesis followed by line-end cutting with additional cut masks. To achieve better yield and manufacturability, the cut patterns shall satisfy specified restricted design rules, and thus it is desirable to develop a novel routing methodology to better address the challenges arising from cut patterns. In this paper, we propose the first nanowire-aware routing system, considering high cut-mask complexity based on a two-pass, bottom-up multilevel routing framework. Experimental results show that our nanowire-aware router can effectively and efficiently reduce cut numbers, cut spacing violations, and line-end extension length.

The directed self-assembly (DSA) technology for next-generation lithography has been shown its great potential for fabricating highly dense via patterns and cut masks in the sub-5 nm technology node and beyond. However, DSA via and cut optimizations were performed independently, which may induce infeasible via and cut templates and spacing violations. It is thus desirable to develop a novel routing system to better address the co-optimization challenges for DSA via and cut templates. In this paper, we propose the first simultaneous DSA via- and cut-template-aware routing system, named VCR, to practically consider both via and cut templates during routing and post-routing based on a two-pass, bottom-up multilevel routing framework. Experimental results show that VCR can effectively reduce via- and cut-template spacing violations.

Two-dimensional (2D) directed self-assembly (DSA) is an emerging lithography for the 5 nm process node and beyond that can substantially increase design flexibility in critical routing layers and reduce the number of cuts for better yield. The state-of-the-art 2D DSA process manipulates the orientation of double posts inside guiding templates to guide block copolymers (BCPs) to form 2D patterns. However, a key challenge arises on how to correctly assign double post orientations and place cut patterns to make desired net connections for a given routing instance. In this paper, we propose a novel 2D DSA-compliant routing framework, named 2D-DCR, to systematically derive feasible orientation assignments for double posts to maximize routability. Specifically, 2D-DCR features a complete set of new routing rules which transform the underlying physical BCP growth principles for large-scale routing, adopts a network-flow-based double-post assignment routing algorithm, and leverages a 2D DSA line-end creation property to maximally reduce line-end cuts. Experimental results show that our 2D-DCR can effectively generate a 2D DSA-compliant routing solution with zero double post conflicts, maximized routability, and minimized the number of cuts.

As nanometer technology advances, conventional optical proximity correction (OPC) that minimizes the edge placement error (EPE) at the nominal process condition alone often leads to poor process windows. To improve the mask printability across various process corners, process-window OPC optimizes EPE for multiple process corners, but often suffers long runtime, due to repeated lithographic simulations. This paper presents an efficient process variation (PV)-aware mask optimization framework, namely PVOPC, to simultaneously minimize EPE and PV band with fast convergence. The PVOPC framework includes EPE-sensitivity-driven dynamic fragmentation, PV-aware EPE modeling, and correction with three new EPE-converging techniques and a systematic subresolution-assisted feature insertion algorithm. Experimental results show that our approach efficiently achieves high-quality EPE and PV band results.

One-dimensional nanowires are one of the most promising next-generation lithography technologies for 7 nm process node and beyond. The 1D nanowire process first constructs a 1D nanoarray through template synthesis followed by line-end cutting with additional cut masks. To achieve better yield and manufacturability, the cut patterns shall satisfy specified restricted design rules, and thus it is desirable to develop a novel routing methodology to better address the challenges arising from cut patterns. In this paper, we propose the first nanowire-aware routing system, called NWR, considering high cut-mask complexity based on a two-pass, bottom-up multilevel routing framework. Experimental results show that our nanowire-aware router can effectively and efficiently reduce cut numbers, cut spacing violations, and line-end extension length.

As nanometer technology advances, conventional OPC (Optical Proximity Correction) that minimizes the EPE (Edge Placement Error) at the nominal corner alone often leads to poor process window. To improve the mask printability across various process corners, process-window OPC optimizes EPE for multiple process corners, but often suffers long runtime, due to repeated lithographic simulations. This paper presents an efficient process-variation-aware mask optimization framework, namely PVOPC (Process-Variation OPC), to simultaneously minimize EPE and PV (Process-Variation) band with fast convergence. The PVOPC framework includes EPE-sensitivity-driven dynamic fragmentation, process-variation-aware EPE modeling, and post correction with three new EPE-converging techniques and a systematic sub-resolution assisted feature insertion algorithm. Experimental results show that our approach efficiently achieves high-quality EPE and PV band results.