This article first proposes a discrete-time sliding flexible performance preset boundary (DT-SFPPB)-based control algorithm for input saturated discrete-time nonlinear systems (IS-DTNSs). Compared to the existing discrete-time prescribed performance control (DT-PPC) algorithms, the PPB of them present a “trumpet” shape, resulting in fundamental conservation of the transient performance, and whenever the initial error is altered, it is essential to recheck whether the new error meets the original constraint condition, if not, a new PPB with a larger measure has to be reselected. By designing a novel DT-SFPPB associated with the initial error, which can always envelope the initial error with an arbitrarily preset initial measure, indicating that the proposed approach can be utilized for IS-DTNSs with arbitrary initial error without compromising the initial transient performance. Furthermore, the coupling effect between performance preset and input saturation is also considered, by designing a novel equilibrium boundary related to saturation, so that the proposed approach can achieve the synergy between performance preset and input security, i.e., the designed DT-SFPPB can flexibly expand when input saturation occurs to avoid vulnerability, and when the control input is within the safe boundary, it rapidly reverts to the original PPB to guarantee the specified performance metrics. The findings demonstrate that the developed approach guarantees that the system output tracks the desired signal with the specified performance metrics, and all of the tracking errors are always enveloped within their corresponding DT-SFPPBs. The devised approach is exemplified by means of simulation examples.

This article first proposes a sliding flexible prescribed performance boundary-guided reinforcement learning (SFPPB-RL) control approach for input-constrained nonlinear systems (ICNSs). By designing a sliding flexible prescribed performance boundary, which not only can adaptively adjust the initial boundary according to the initial error, but also dynamically adjust the constraint relaxation according to the coupling correlation between the input constraint and the performance constraint, a novel prescribed performance control (PPC) approach is proposed. Compared with the existing "horn" shape performance boundary-based PPC methods, the limitation of having to repeatedly debug design parameters or sacrifice initial transient performance to meet different initial error requirements is eliminated. Meanwhile, the coupling effect between the input constraint and the performance constraint is also considered, and the balance between input safety and control performance is achieved by constructing an auxiliary system. Furthermore, combining identifier-critic-actor structure-based RL strategy and backstepping technique, a sliding flexible PPB-guided reinforcement learning (SFPPB-RL) optimal control algorithm is developed, which minimizes the cost function while ensuring input safety and prescribed performance indicators. The validity of the proposed algorithm is demonstrated via simulations.

There has been a growing interest in applying machine learning to real-world tasks. However, due to the black-box nature of machine learning models, it is crucial to 1) verify important properties of a model and 2) understand the reasons behind a model’s prediction before deploying them in a production environment. Existing approaches typically handle them as two separate and sometimes orthogonal topics. In this paper, we show that the verification and interpretability of machine learning models are tightly related and can be unified by satisfiability modulo theories (SMT). Our key insight is: not only a wide range of properties of machine learning models can be formulated as SMT problems and verified accordingly, but many commonly studied interpretability questions can also be answered by iteratively checking the satisfiability and related properties of multiple SMT problems. Leveraging this insight, we design UINT, a general verification and interpretability framework for learning-based networking systems. UINT 1) allows operators to specify verification and interpretability problems as SMT formulas, 2) encodes the target machine learning models into SMT constraints, and 3) automatically simplifies and solves the corresponding verification and interpretability problems using commodity SMT solvers. We implement a prototype of UINT and evaluate it on real-world learning-based networking systems. Results demonstrate the efficiency and efficacy of UINT in verifying and interpreting key questions for these systems.

Multiple systems have explored how to use programmable switch ASICs to improve the performance of distributed systems. However, they focus on accelerating read operations and perform poorly under write-intensive workloads. In this paper, we present Gecko, a system that accelerates write operations in distributed key-value store systems using switch ASICs. The core idea of Gecko is to offload the client-side chasing mechanism, a technique deployed by production storage networks, to the programmable switch to simultaneously reduce the perceived and actual write-tail latency in distributed key-value stores. The perceived latency is the interval between the user sending a write request and the user receiving the write success, and there may be replicas that have not yet completed the write, but the actual latency requires all replicas to be successfully written. Gecko not only reduces the perceived write tail latency by deploying the chasing mechanism, but the actual write tail latency is also reduced by utilizing the capabilities of programmable switches. Specifically, Gecko’s in-network chasing design caches a write request at the switch data plane and reports success to the client when only m out of n (usually set to 2 and 3 in production networks, respectively) replicas have been successfully written to the server, and retries the cached write request if the remaining n − m replicas are not successfully written. In addition to caching the write request, Gecko also introduces novel designs to fully implement the chasing controller and a corresponding timer controller in the switch data plane, minimizing the interaction overhead between the switch control and data plane. Extensive experiments on a testbed of Barefoot Tofino switch and commodity servers show that Gecko not only substantially reduces the write tail latency by more than 2.16x caused by transient glitches at servers, but also maintains the same level of reliability as the classic three-replica write operation in distributed key-value stores.

Abstract This paper pays close attention to the stabilization issue for delayed uncertain semi-Markovian jumping complex-valued networks via sliding mode control. The concerned corresponding transition rates depend on a positive constant, i.e., sojourn-time, which is not required to obey the general exponential distribution. Combine the generalized Dynkin’s formula with Lyapunov stability theory as well as the characteristics of cumulative distribution functions, a few sufficient criteria are proposed to ascertain the stochastic stability of the obtained sliding mode dynamical system. In addition, design a novel sliding mode controller to ensure all state trajectories of the potential closed-loop system can reach the synthesized sliding mode switching surface in a finite time and maintain there in the subsequent time. In the end of paper, one simple example is presented to verify superiority and feasibility of the provided controller design scheme.

There has been a growing interest in applying machine learning to real-world tasks. However, due to the blackbox nature of machine learning models, it is crucial to (1) verify important properties of a model and (2) understand the reasons behind a model's prediction before deploying them in a production environment. Existing approaches typically handle them as two separate and sometimes orthogonal topics. In this paper, we show that the verification and interpretability of machine learning models are tightly related and can be unified by satisfiability modulo theories (SMT). Our key insight is: not only a wide range of properties of machine learning models can be formulated as SMT problems and verified accordingly, but many commonly studied interpretability questions can also be answered by iteratively checking the satisfiability and related properties of multiple SMT problems. Leveraging this insight, we design UINT, a general verification and interpretability framework for learning-based networking systems. UINT (1) allows operators to specify verification and interpretability problems as SMT formulas, (2) encodes the target machine learning models into SMT constraints, and (3) automatically solves the corresponding verification and interpretability problems using commodity SMT solvers. We implement a prototype of UINT and evaluate it on real-world learning-based networking systems. Results demonstrate the efficiency and efficacy of UINT in verifying and interpreting key questions for these systems.

In-memory key-value store is a crucial building block of large-scale web architecture. Given the growth of the data volume and the need for low-latency responses, cost-effective storage expansion and fast large-message processing are the major challenges. In this paper, we explore the design of key-value middleware that takes advantage of modern NVMe SSDs and RDMA interconnects to achieve high performance without excessive DRAM deployment. We propose an all-in-userland approach to improve the data plane efficiency. Both NVMe and RDMA are interfaced directly from the user-space for effective data access and tailored data management. We present a low-latency storage extension framework based on NVMe and a new design of JVM-aware Memcache protocol based on RDMA. To further accelerate large-message transfer, we provide a hybrid communication protocol fusing Eager and Rendezvous schemas, and a united I/O staging approach to achieve maximum latency hiding through pipelining. As the benchmarking results indicate, with the non-negligible JVM overhead taken into account, our solution obtains comparable communication performance with the RDMA-Memcached released by the OSU. For SSD-involved operations, the latency decreases by up to 31% compared to the kernel-based I/O processing.

Heterogeneous Computing is becoming an important technology trend in HPC, where more and more heterogeneous processors are used. However, in traditional node architecture, heterogeneous processors are always used as coprocessors. Such usage increases the communication latency between heterogeneous processors and prevents the node from achieving high density. With the purpose of improving communication efficiency between heterogeneous processors, this paper proposed a new node architecture named HeteNode. In HeteNode, general purpose processors and heterogeneous processors are interconnected by a system controller directly and play the same role in both process of communication and process of computation. The prototype of HeteNode which contains nine processors in 1U chassis is built. Evaluation carried out on the prototype shows that 580ns minimum intra-node latency and 1.78us minimum inter-node latency between heterogeneous processors are achieved. Besides, NPB benchmarks show good scalability in HeteNode.

MPI All to all communication is widely used in many high performance computing (HPC) applications. In All to all communication, each process sends a distinct message to all other participating processes. In multicore clusters, processes within a node simultaneously contend for the same network resource of the node in All to all communication. However, many small synchronization messages are required in All to all communication of large messages. With the contention, their latency is orders of magnitude larger than that without contention. As a result, the synchronization overhead is significantly increased and accounts for a large proportion to the whole latency of All to all communication. In this paper, we analyse the considerable overhead of synchronization messages. Base on the analysis, an optimization is presented to reduce the number of synchronization messages from 3N to 2¡ÌN. Evaluations on a 240-core cluster show that the performance is improved by almost constant ratio, which is mainly determined by message size and independent of system scale. The performance of All to all communication is improved by 25% for 32K and 64K bytes messages. For FFT application, performance is improved by 20%.

Heterogeneity is considered as a solution for supercomputers to scale to petascale. Many systems which are composed of general CPUs and special processing units such as Cells, GPGPUs and FPGAs have been implemented. In these systems, CPU needs interact with special processing units to process data together, thus communications between these heterogeneous processing units become a key problem, and the communication subsytem should provide low latency and high bandwidth. In this paper, we propose HPP-Controller, which is designed for connecting two different types of CPUs (AMD and Loongson) in one node. It connects heterogeneous CPUs on top of no-coherent HyperTransport (HT) fabric and supports Global Physical Address Space. We implement a FPGA-based prototype and evaluate it via experiments. Initial Results show that HPP-Controller has low latency of 0.75us and high bandwidth close to bandwith of HT links.