VLDB 2026 Research / reviewers in the wild / expert
John Harrison 0001
dblp:72/960-1 · also John R. Harrison
· DBLP profile ↗
32ranked-venue papers
21as first author
1since 2021 · last 2026
0000-0001-5707-4631ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Theory of computation · 19 · 16 first-authorArtificial intelligence and machine learning · 9 · 8 first-authorSoftware engineering, systems software and programming languages · 6 · 4 first-authorSystems, architecture and hardware · 3Applied, interdisciplinary, general and emerging computing · 2 · 1 first-authorSecurity and privacy · 1 · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
1 paper |
Cryptographic primitives and cryptanalysis · 77% Hardware security and side channels · 23% | |
| Computer architecture, parallel and distributed computing, and storage systems
4 papers |
Integrated circuit design · 64% Processor architecture and microarchitecture · 20% Electronic design automation · 10% | |
| Software engineering, system software, and programming languages
2 papers |
Program verification · 83% Programming languages and type systems · 17% |
Topics — the 19 heaviest of 21, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Cryptographic primitives and cryptanalysis › cryptographic implementation
constant-time implementation |
1.0 | 1 | 2026 | Accelerating and verifying constant-time modular inversion · EUROCRYPT (7) 2026 |
Cryptographic primitives and cryptanalysis › finite field arithmetic
modular inversion |
1.0 | 1 | 2026 | Accelerating and verifying constant-time modular inversion · EUROCRYPT (7) 2026 |
Integrated circuit design › digital circuit design
arithmetic circuit design |
0.3 | 1 | 2018 | Digit Serial Methods with Applications to Division and Square Root · IEEE Trans. Computers 2018 |
Integrated circuit design › digital arithmetic circuits
division and square root |
0.3 | 1 | 2018 | Digit Serial Methods with Applications to Division and Square Root · IEEE Trans. Computers 2018 |
Hardware security and side channels
side-channel attack |
0.3 | 1 | 2026 | Accelerating and verifying constant-time modular inversion · EUROCRYPT (7) 2026 |
Hardware security and side channels › side-channel attack
timing side channel |
0.3 | 1 | 2026 | Accelerating and verifying constant-time modular inversion · EUROCRYPT (7) 2026 |
Program verification
verification |
0.1 | 1 | 2011 | Robin Milner 1934--2010: verification, languages, and concurrency · POPL 2011 |
Processor architecture and microarchitecture › computer arithmetic
floating-point arithmetic |
0.1 | 2 | 2009 | A Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic Using the Binary Encoding Format · IEEE Trans. Computers 2009 Formal Verification at Intel · LICS 2003 |
Processor architecture and microarchitecture › computer arithmetic
decimal floating-point arithmetic |
0.1 | 1 | 2009 | A Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic Using the Binary Encoding Format · IEEE Trans. Computers 2009 |
Integrated circuit design › digital arithmetic circuits › floating-point unit design
rounding |
0.1 | 1 | 2009 | A Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic Using the Binary Encoding Format · IEEE Trans. Computers 2009 |
Automated reasoning and model checking
theorem proving |
0.1 | 1 | 2008 | Theorem Proving for Verification (Invited Tutorial) · CAV 2008 |
Program verification › hardware verification
floating-point verification |
0.1 | 1 | 2005 | Floating-Point Verification · FM 2005 |
Electronic design automation › hardware verification and test
formal verification |
0.0 | 1 | 2003 | Formal Verification at Intel · LICS 2003 |
Electronic design automation › hardware verification and test
hardware verification |
0.0 | 1 | 2003 | Formal Verification at Intel · LICS 2003 |
Electronic design automation › hardware verification and test › formal verification
theorem proving |
0.0 | 1 | 2003 | Formal Verification at Intel · LICS 2003 |
Programming languages and type systems
language design |
0.0 | 1 | 2011 | Robin Milner 1934--2010: verification, languages, and concurrency · POPL 2011 |
Processor architecture and microarchitecture
instruction set architecture |
0.0 | 1 | 2001 | Scientific computing on the Itanium processor · SC 2001 |
High-performance computing › numerical linear algebra
linear algebra kernel |
0.0 | 1 | 2001 | Scientific computing on the Itanium processor · SC 2001 |
High-performance computing
scientific computing systems |
0.0 | 1 | 2001 | Scientific computing on the Itanium processor · SC 2001 |
Methods — techniques the papers use, named apart from their topics
formal verification · 1.0constant-time programming · 1.0error bound analysis · 0.3software emulation · 0.1binary encoding · 0.1theorem proving · 0.1LCF-style theorem proving · 0.0HOL Light · 0.0performance modeling · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Accelerating and verifying constant-time modular inversion
Daniel J. Bernstein, Han-Ting Chen, John Harrison 0001, Cesare Huang, Gregory Maxwell, Bow-Yaw Wang, Pieter Wuille, Bo-Yin Yang |
EUROCRYPT (7) | 3 |
| 2018 | Digit Serial Methods with Applications to Division and Square RootabstractWe present a generic digit serial method (DSM) to compute the digits of a real number V. Bounds on these digits, and on the errors in the associated estimates of V formed from these digits, are derived. To illustrate our results, we derive such bounds for a parameterized family of high-radix algorithms for division and square root. These bounds enable a DSM designer to determine, for example, whether a given choice of parameters allows rapid formation and rounding of its approximation to V. Warren E. Ferguson, Jesse Bingham, Levent Erkök, John Harrison 0001, Joe Leslie-Hurd |
IEEE Trans. Computers | 4 |
| 2015 | Formal Proofs of Hypergeometric Sums - Dedicated to the memory of Andrzej Trybulec
John Harrison 0001 |
J. Autom. Reason. | 1 |
| 2013 | The HOL Light Theory of Euclidean Space
John Harrison 0001 |
J. Autom. Reason. | 1 |
| 2012 | Some new results on decidability for elementary algebra and geometry
Robert Solovay, Rob Arthan, John Harrison 0001 |
Ann. Pure Appl. Log. | 3 |
| 2011 | Robin Milner 1934--2010: verification, languages, and concurrencyabstractNo abstract available. Andrew D. Gordon 0001, Robert Harper 0001, John Harrison 0001, Alan Jeffrey, Peter Sewell |
POPL | 3 |
| 2011 | A formal proof of Pick's TheoremabstractPick's Theorem relates the area of a simple polygon with vertices at integer lattice points to the number of lattice points in its inside and boundary. We describe a formal proof of this theorem using the HOL Light theorem prover. As sometimes happens for highly geometrical proofs, the formalisation turned out to be more work than initially expected. The difficulties arose mostly from formalising the triangulation process for an arbitrary polygon. John Harrison 0001 |
Math. Struct. Comput. Sci. | 1 |
| 2010 | Verifying a Synthesized Implementation of IEEE-754 Floating-Point Exponential Function using HOLabstractDeep datapath and algorithm complexity have made the verification of floating-point units a very hard task. Most simulation and reachability analysis verification tools fail to verify a circuit with a deep datapath like most industrial floating-point units. Theorem proving, however, offers a better solution to handle such verification. In this paper, we have hierarchically formalized and verified a hardware implementation of the IEEE-754 table-driven floating-point exponential function algorithm using the higher-order logic (HOL) theorem prover. The high ability of abstraction in the HOL verification system allows its use for the verification task over the whole design path of the circuit, starting from gate-level implementation of the circuit up to a high-level mathematical specification. Behzad Akbarpour, Amr Talaat Abdel-Hamid, Sofiène Tahar, John Harrison 0001 |
Comput. J. | 4 |
| 2010 | A Revision of the Proof of the Kepler Conjecture
Thomas C. Hales, John Harrison 0001, Sean McLaughlin, Tobias Nipkow, Steven Obua, Roland Zumkeller |
Discret. Comput. Geom. | 2 |
| 2009 | Fast and Accurate Bessel Function ComputationabstractThe Bessel functions are considered relatively difficult to compute. Although they have a simple power series expansion that is everywhere convergent, they exhibit approximately periodic behavior which makes the direct use of the power series impractically slow and numerically unstable. We describe an alternative method based on systematic expansion around the zeros, refining existing techniques based on Hankel expansions, which mostly avoids the use of multiprecision arithmetic while yielding accurate results. John Harrison 0001 |
IEEE Symposium on Computer Arithmetic | 1 |
| 2009 | Decimal Transcendentals via BinaryabstractWe describe the design and implementation of a comprehensive library of transcendental functions for the new IEEE decimal floating-point formats. In principle, such functions are very much analogous to their binary counterparts,though with a few additional subtleties connected with 'scale' (preferred exponent). But our approach has been not to employ direct techniques, but rather to re-use existing binary functions as much as possible, both for greater efficiency and ease of implementation. For some functions the most straightforward approach (convert from decimal to binary, perform binary operation, convert back) works well. In many cases, however, these are insufficiently accurate, and subtler approaches must be used. John Harrison 0001 |
IEEE Symposium on Computer Arithmetic | 1 |
| 2009 | Formalizing an Analytic Proof of the Prime Number Theorem
John Harrison 0001 |
J. Autom. Reason. | 1 |
| 2009 | A Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic Using the Binary Encoding FormatabstractThe IEEE Standard 754-1985 for binary floating-point arithmetic [19] was revised [20], and an important addition is the definition of decimal floating-point arithmetic [8], [24]. This is intended mainly to provide a robust reliable framework for financial applications that are often subject to legal requirements concerning rounding and precision of the results, because the binary floating-point arithmetic may introduce small but unacceptable errors. Using binary floating-point calculations to emulate decimal calculations in order to correct this issue has led to the existence of numerous proprietary software packages, each with its own characteristics and capabilities. The IEEE 754R decimal arithmetic should unify the ways decimal floating-point calculations are carried out on various platforms. New algorithms and properties are presented in this paper, which are used in a software implementation of the IEEE 754R decimal floating-point arithmetic, with emphasis on using binary operations efficiently. The focus is on rounding techniques for decimal values stored in binary format, but algorithms are outlined for the more important or interesting operations of addition, multiplication, and division, including the case of nonhomogeneous operands, as well as conversions between binary and decimal floating-point formats. Performance results are included for a wider range of operations, showing promise that our approach is viable for applications that require decimal floating-point calculations. This paper extends an earlier publication [6]. Marius Cornea, John Harrison 0001, Cristina Anderson, Ping Tak Peter Tang, Eric Schneider, Evgeny Gvozdev |
IEEE Trans. Computers | 2 |
| 2008 | Theorem Proving for Verification (Invited Tutorial)
John Harrison 0001 |
CAV | 1 |
| 2007 | A Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic Using the Binary Encoding FormatabstractThe IEEE Standard 754-1985 for binary floating-point arithmetic [1] was revised [2], and an important addition is the definition of decimal floating-point arithmetic. This is intended mainly to provide a robust, reliable framework for financial applications that are often subject to legal requirements concerning rounding and precision of the results, because the binary floating-point arithmetic may introduce small but unacceptable errors. Using binary floating-point calculations to emulate decimal calculations in order to correct this issue has led to the existence of numerous proprietary software packages, each with its own characteristics and capabilities. IEEE 754R decimal arithmetic should unify the ways decimal floating-point calculations are carried out on various platforms. New algorithms and properties are presented in this paper which are used in a software implementation of the IEEE 754R decimal floatingpoint arithmetic, with emphasis on using binary operations efficiently. The focus is on rounding techniques for decimal values stored in binary format, but algorithms for the more important or interesting operations of addition, multiplication, division, and conversions between binary and decimal floating-point formats are also outlined. Performance results are included for a wider range of operations, showing promise that our approach is viable for applications that require decimal floating-point calculations. Marius Cornea, Cristina Anderson, John Harrison 0001, Ping Tak Peter Tang, Eric Schneider, Charles Tsen |
IEEE Symposium on Computer Arithmetic | 3 |
| 2007 | Automating Elementary Number-Theoretic Proofs Using Gröbner Bases
John Harrison 0001 |
CADE | 1 |
| 2005 | A Proof-Producing Decision Procedure for Real Arithmetic
Sean McLaughlin, John Harrison 0001 |
CADE | 2 |
| 2005 | Floating-Point Verification
John Harrison 0001 |
FM | 1 |
| 2003 | Isolating Critical Cases for Reciprocals Using Integer FactorizationabstractOne approach to testing and/or proving correctness of a floating-point algorithm computing a function f is based on finding input floating-point numbers a such that the exact result f(a) is very close to a "rounding boundary", i.e. a floating-point number or a midpoint between them. We show how to do this for the reciprocal function by utilizing prime factorizations. We present the method and show examples, as well as making a fairly detailed study of its expected and worst-case behavior. We point out how this analysis of reciprocals can be useful in analyzing certain reciprocal algorithms, and also show how the approach can be trivially adapted to the reciprocal square root function. John Harrison 0001 |
IEEE Symposium on Computer Arithmetic | 1 |
| 2003 | Formal Verification at IntelabstractAs designs become more complex, formal verification techniques are becoming increasingly important in the hardware industry. Many different methods are used, ranging from propositional tautology checking up to use of interactive higher-order theorem provers. Our own work is mainly concerned with the formal verification of floating-point mathematical functions. As this paper illustrates, such applications require a rather general mathematical framework and the ability to automate special-purpose proof algorithms in a reliable way. Our work uses the public-domain interactive theorem prover HOL Light, and we claim that this and similar 'LCF-style' theorem provers are a good choice for such applications. John Harrison 0001 |
LICS | 1 |
| 2003 | Formal Verification of Square Root Algorithms
John Harrison 0001 |
Formal Methods Syst. Des. | 1 |
| 2002 | Enabling Hardware Verification through Design Changes
Amr Talaat Abdel-Hamid, Sofiène Tahar, John Harrison 0001 |
ICFEM | 3 |
| 2001 | Scientific computing on the Itanium processorabstractThe 64-bit Intel® Itanium™ architecture is designed for high-performance scientific and enterprise computing, and the Itanium processor is its first silicon implementation. Features such as extensive arithmetic support, predication, speculation, and explicit parallelism can be used to provide a sound infrastructure for supercomputing. A large number of high-performance computer companies are offering Itanium™-based systems, some capable of peak performance exceeding 50 GFLOPS. In this paper we give an overview of the most relevant architectural features and provide illustrations of how these features are used in both low-level and high-level support for scientific and engineering computing, including transcendental functions and linear algebra kernels. Bruce Greer, John Harrison 0001, Greg Henry, Wei Wayne Li, Ping Tak Peter Tang |
SC | 2 |
| 2000 | High-Level Verification Using Theorem Proving and Formalized Mathematics
John Harrison 0001 |
CADE | 1 |
| 2000 | Formal Verification of Floating Point Trigonometric Functions
John Harrison 0001 |
FMCAD | 1 |
| 2000 | Floating Point Verification in HOL Light: The Exponential Function
John Harrison 0001 |
Formal Methods Syst. Des. | 1 |
| 1998 | A Skeptic's Approach to Combining HOL and Maple
John Harrison 0001, Laurent Théry |
J. Autom. Reason. | 1 |
| 1996 | Optimizing Proof Search in Model Elimination
John Harrison 0001 |
CADE | 1 |
| 1996 | HOL Light: A Tutorial Introduction
John Harrison 0001 |
FMCAD | 1 |
| 1995 | Binary Decision Diagrams as a HOL Derived RuleabstractBinary Decision Diagrams (BDDs) are a representation for Boolean formulas which makes many operations, in particular tautology-checking, surprisingly efficient in important practical cases. In contrast to such custom decision procedures, the HOL theorem prover expands all proofs out to a sequence of extremely simple primitive inferences. In this paper we describe how the BDD algorithm may be adapted to comply with such strictures, helping us to understand the strengths and limitations of the HOL approach. John Harrison 0001 |
Comput. J. | 1 |
| 1994 | Constructing the Real Numbers in HOL
John Harrison 0001 |
Formal Methods Syst. Des. | 1 |
| 1993 | Reasoning About the Reals: The Marriage of HOL and Maple
John Harrison 0001, Laurent Théry |
LPAR | 1 |