This paper proposes an algorithm to aid in the characterization of a printed circuit board fabrication process before the design of microstrip circuits. By accurately characterizing the electrical properties of a printed circuit board process, one can achieve a systematic and efficient design of microstrip circuits with reduced iteration cycles. The algorithm employs a mean-squared-error optimization technique while making use of de-embedded scattering parameter data from some sample microstrip transmission lines, to estimate printed circuit board electrical parameters such as the tangent loss and the relative permittivity, for a particular frequency range.

This paper presents the design and implementation of a Simple Network Management Protocol RF power monitoring system for a 1.5 kW Air Traffic Control high power amplitude modulation transmitter operating at 122.775 MHz. The design is centered around an optimized four port microstrip directional coupler which enables the monitoring of the forward power and the reflected power in the transmitter RF chain. Optimization was focused on its coupling, directivity and isolation. The designed dual directional coupler features a measured coupling of -25 dB, a directivity of 41 dB, and an isolation between the forward and reverse coupling paths of around -70 dB, over the air band (118 MHz to 137 MHz). The forward and reflected power signals are converted to low voltage baseband signals via a logarithmic amplifier to enable further processing via a microcontroller platform. The implemented system provides parameters such as the modulation index, forward and reflected power, standing wave ratio and reflection coefficient, via a dedicated Simple Network Management Protocol over a local area network. The proposed system also provides an alarm in case an increase in the standing wave ratio above a certain threshold is detected.

In this paper, the design, implementation and evaluation of a hybrid Sudoku puzzle solver on a Field-Programmable Gate Array (FPGA) is presented. The solver initially makes use of pen-and-paper solving techniques to reduce the number of possible values and prune the overall search space. Once this process is complete, the solver then utilizes a depth-first search algorithm to systematically guess and backtrack through the puzzle, until a solution is reached. This work strived to implement a solver with minimal area utilization while maintaining simplicity and still achieving adequate performance. The implementation and the testing of the Sudoku puzzle solver were carried out on a Xilinx Spartan-6 XC6SLX45 FPGA.

This paper presents the measured results and characterization of a fabricated power conditioning and energy storage integrated circuit for energy harvesters with on-chip maximum power point tracking (MPPT). This ultra-low power circuit employs an AC/DC-to-DC converter to be compatible with both AC and DC voltage energy harvesters, and features a wide input voltage and power range. The circuit was implemented using the AMS CMOS 0.35 μm high voltage technology and all the circuit blocks were designed using analog electronic techniques, with the transistors operating in the sub-threshold region, in order to obtain a minimum power consumption. In fact, this power conditioning circuit consumes less than 2 μW while featuring an input voltage range of ±0.5V to ±50V and a power range of 10μW to 200 mW.

This paper illustrates the use of the Particle Swarm Optimization (PSO) algorithm to maximize the linearity of a rail-to-rail delay element. Previous approaches relied on approximating the piecewise time-delay model of the delay element through either the Newton Polynomial or the Lagrange Polynomial methods. While adequate linearity was achieved in both cases, this could be further improved. This work successfully employed the PSO algorithm to improve the linearity by reducing the mean square error such that the delay element exhibits a spurious-free dynamic range of 29.62 dB, with a delay range of 170.4 ns. The results were verified in Cadence using the X-FAB 0.18 μm technology.

This paper presents the hardware implementation of a differential coded Smith-Waterman algorithm on a field programmable gate array (FPGA). A novel path reconstruction algorithm is proposed to overcome the need of a dedicated memory for the storage of the similarity matrix, thus limiting the on-chip hardware utilization. In addition, this algorithm is also efficient in terms of computational speed since the path reconstruction is carried out during the computation of the similarity score, rather then afterwards, as in the case of the original algorithm. The implementation was done on the Xilinx Spartan-6 XC6LX16-CS324 FPGA using VHDL, consisting of 1,024 processing elements and exhibits a throughput of 204.8 BCUPS at a data rate of 600 Mbps.

Over the past decades, extensive research has been carried out on various possible implementations of automatic speech recognition (ASR) systems. The most renowned algorithms in the field of ASR are the mel‐frequency cepstral coefficients and the hidden Markov models. However, there are also other methods, such as wavelet‐based transforms, artificial neural networks and support vector machines, which are becoming more popular. This review article presents a comparative study on different approaches that were proposed for the task of ASR, and which are widely used nowadays.