The object of this paper is to analyze the potential benefits of conducting a BIST pretest before launching a functional test of ICs during post manufacturing screening. In (Nakamura et al., 2005) the impact of BIST on the chip defect level after test has been addressed. It was assumed in (Nakamura et al., 2005) that no measures are taken to assure that the BIST circuitry is fault-free before launching the functional test. In this paper, we assume that a BIST pretest is first conducted in order to rid of all chips that fail it. Only chips whose BIST circuitry has passed the pretest are kept, while the rest are discarded. The BIST pretest, however, is assumed to have only a limited coverage against its own faults. This paper studies the product quality improvements as induced by the BIST pretest, and provides some insight as to when this pretest maybe worthwhile performing. As the study shows, in many cases the potential benefits outweigh any potential risks

This paper proposes two power-constrained test synthesis schemes and scheduling algorithms, under non-scan BIST, for RTL data paths. The first scheme uses boundary non-scan BIST, and can achieve a low hardware overhead. The second scheme uses generic non-scan BIST, and can offer some tradeoffs between hardware overhead, test application time and power dissipation. A designer can easily select an appropriate design parameter based on the desired tradeoff. Experimental results confirm good performance and practicality of our approaches.

Coefficient-based test (CBT) is introduced for de- tecting parametric faults in analog circuits. The method uses pseudo Monte- Carlo simulation and system identiscation tools to determine whether a given circuit under test (CUT) is faulty.

This paper investigates the detectability of parameter faults in linear, time-invariant, analog circuits. We show that there are inherent limitations with regard to analog faults detectability.

This paper investigates the detectability of parameter faults in linear, time-invariant, analog circuits. We show that there are inherent limitations with regard to analog fault detectability.

Testing and characterization of analog circuits is a very important task in the VLSI manufacturing process. However, no efficient methodology exists on how to effectively model and characterize the various faults, and even how to detect their existence. Neural networks have been successfully applied to various pattern recognition problems. In this paper, the amplitude and temporal characteristics of the good circuit response are used to train a neural network, so that it is able to distinguish between different faulty circuit responses. A Time-Delay Neural Network (TDNN) is proposed as a possible vehicle for performing the test and diagnosis.

This paper deals with studying the effects of both online and off-line test during flight critical missions where safety is a major issue. The on-line test, in this context, is a test performed on a digital airborne system during some specified windows in time while it is still performing its intended task. An off-line test is a test that is performed on the digital system once it is taken off-line because of a suspected failure. Both the on-line and the off-line tests are performed during flight. The difference between the two is that the off-line test can be made more effective than the on-line test due to the longer amount of time available for testing. Moreover, the off-line test may be designed to have diagnosis and repair capabilities built-in. Upon successful repair, the faulty processor may be reconfigured back into the system. This capability will undoubtedly increase the mission reliability.

In this paper we present MUST-a multiple-stem analysis algorithm for identifying untestable faults in sequential circuits. In general, processing untestable faults is the most time-consuming part of a sequential ATPG. MUST extends the scope of the single-stem analysis done in the FIRES algorithm by identifying additional untestable faults that cannot be found by single-stem analysis. While its computational requirements are greater than those of FIRES, the run-time of MUST remains significantly lower than that used by sequential ATPG. We show that the faults identified by MUST are difficult targets for conventional ATPG programs, that can benefit by using MUST as a preprocessor and excluding the untestable faults identified by multiple stem analysis from the target faults processed by ATPG. We report experimental results obtained by our prototype implementation of MUST on ISCAS benchmarks and other circuits.

This paper deals with studying the effects of both on-line and off-line test during flight critical missions where safety is a major issue. The on-line test, in this context, is a test performed on a digital airborne system during some specified windows in time while it is still performing its intended task. An off-line test is a test that is performed on the digital system once it is taken, off-line because of a suspected failure. Both the on-line and the off-line tests are performed during flight. The difference between the two is that the off-line test can be made more effective than an on-line test due to the longer amount of time available for testing. Moreover, the off-line test may be designed to have diagnosis and repair capabilities built-in. Upon successful repair, the faulty processor may be reconfigured back into the system. This capability will undoubtedly increase the mission reliability.

This paper describes a random access memory (RAM, sometimes also called an array) test scheme that has the following attributes: 1. Can be used in both built-in mode and off chip/module mode. 2. Can be used to test and diagnose naked arrays. 3. Fault diagnosis is simple and is "free" for some faults during test. 4. Is never subject to aliasing. 5. Depending upon the test length, it can detect many kinds of failures, like stuck-cells, decoder faults, shorts, pattern-sensitive, etc. 6. If used as a built-in feature, it does not slow down the normal operation of the array. 7. Does not require storage of correct responses. A single response bit always indicates whether a fault has been detected. Thus, the storage requirement for the implementation of the test scheme is zero. 8. If used as a built-in feature, the hardware overhead is very low.

To successfully combat delay faults there is an urgent need for a proper design for testability (DFT). The foundation of any DFT methodology rests on its scan design. The paper describes a new design of a shift register latch that lends itself to distributed self-test and delay test. The advantages of this new SRL is faster application of test vectors, higher DC and AC fault coverages, with low performance impact. Operation, cost, and other attributes are studied in detail. Results of adopting this SRL are reported on ten pilot chips.

This paper describes the design details, operation, cost, and performance of a distributed weighted pattern test approach at the chip level. The traditional LSSD SRLs are being replaced by WRP SRLs designed specifically to facilitate a weighted random pattern (WRP) test. A two-bit code is transmitted to each WRP SRL to determine its specific weight. The WRP test is then divided into groups, where each group is activated with a different set of weights. The weights are dynamically adjusted during the course of the test to "go after" the remaining untested faults. The cost and performance of this design system are explored on ten pilot chips. Results of this experiment are provided in the paper.

An efficient method is described for using fault simulation as a solution to the diagnostic problem created by the presence of embedded memories in BIST designs. The idea is to create simulation models that only use combinational logic (i.e., the memory is removed).

A new weighted random pattern (WRP) design for testability (DFT) is described where the shift register latches (SRLs) distributed throughout the chip are modified so that they can generate biased pseudo-random patterns upon demand. A two-bit code is transmitted to each WRP SRL to determine its specific weight. The WRP test is then divided into groups, where each group is activated with a different set of weights. The weights are dynamically adjusted during the course of the test to "go after" the remaining untested faults. The cost and performance of this design system are explored on three pilot chips. Results of this experiment are provided in the paper.

This paper analyzes the random pattern testability of faults in the control logic of an embedded memory. We show how to compute exposure probabilities of these faults using mostly signal probability computations. We also show that the hardest memory control logic fault to detect is not necessarily the one with the lowest detection probability at the memory boundary.

This paper uses the STUMPS architecture to study the properties of a new diagnostic procedure. According to the old procedure, the process stops at the end of each test window to compare the measured signature against its precomputed value. The old procedure also calls for the abandonment of all future test windows after the first failing one is encountered. This is due to the unavailability of expected future test window signatures in the presence of a previously captured error. This paper shows a simple method of salvaging future test windows by adjusting their expected signatures to fit past observed errors. Experiments conducted using this new procedure reveal an improvement of at least one order of magnitude in diagnostic resolution over what has been previously experienced.

An analytical method is described for determining the random pattern testability of faults in combinational logic feeding the address inputs of embedded memories. Difference information from replicated copies of embedding logic is used to determine the probability of detecting any fault in the upstream of either a read or write port address decoder. The method can be used with minor extensions to existing detection probability tools such as the cutting algorithm.

This paper shows that when it comes to complementary metal-oxide-semiconductor (CMOS) designs undetectability does not necessarily imply redundancy. The definition of redundancy is extended to account for the special behavior encountered in CMOS designs. The accuracy of the new redundancy definition has been tested on several CMOS chips and has been found to be correct.

This paper shows a new family of shift register designs which enjoys a reduced latch count. Reduction in the latch count is achieved by introducing additional clocks. The reduction in latch count may reach the ultimate savings of 50%.

This paper describes the design details, operation, cost, and performance of a distributed weighted pattern test approach at the chip level. The traditional LSSD SRLs are being replaced by WRP SRLs designed specifically to facilitate a weighted random pattern (WRP) test. A two-bit code is transmitted to each WRP SRL to determine its specific weight. The WRP test is then divided into groups, where each group is activated with a different set of weights. The weights are dynamically adjusted during the course of the test to "go after" the remaining untested faults. The cost and performance of this design system are explored on three pilot chips. Results of this experiment are provided in the paper.

An efficient method is described for using fault simulation as a solution to the diagnostic problem created by the presence of embedded memories in BIST designs. The simulation is event-table-driven. Special techniques are described to cope with the faults in the Prelogic, Postlogic, and the logic embedding the memory control or address inputs. It is presumed that the memory itself has been previously tested, using automatic test pattern generation (ATPG) techniques via the correspondence inputs, and has been found to be fault-free.

This paper describes three new designs of a shift register latch that lend themselves to distributed self-test and delay test. The advantages of these new SRLs are faster application of test vectors, higher DC and AC fault coverages, with low performance impact. Operation, cost, and other attributes are studied in detail. Results of adopting one of the new SRLs are reported on three pilot chips.

This paper analyzes the random pattern testability of faults in the control logic of an embedded memory. We show how to compute exposure probabilities of these faults using mostly signal probability computations. We also show that the hardest memory control logic fault to detect is not necessarily the one with the lowest detection probability at the memory boundary.

This paper uses the STUMPS architecture to study the properties of a new diagnostic procedure. According to the old procedure the process stops at the end of each test window to compare the measured signature against its precomputed value. The old procedure also calls for the abandonment of all future test windows after the first failing one is encountered. This is due to the unavailability of expected future test window signatures in the presence of a previously captured error. This paper shows a simple method of salvaging future test windows by adjusting their expected signatures to fit past observed errors. Experiments conducted using this new procedure reveals an improvement of at least one order of magnitude in diagnostic resolution over what has been previously experienced.

Multiple-input signature registers (MISRs) are commonly used in built-in self-test (BIST) applications. The size of the MISR is dictated by the number of signals it has to compress. Normally a MISR includes a stage for every signal that it is sampling. In some applications this leads to very wide MISRs that may include several hundred stages. Large size MISRs pose problems in terms of hardware and wiring overhead. Shorter compressors are, therefore, needed. This paper investigates the problem of reducing the MISR so that it samples multiple signals at every stage. Issues like detection probability loss, test length penalty, fault coverage degradation, are some of the disadvantages that may arise from the MISR shrinkage. This paper analyzes all these issues; shows ways to reduce their negative effect, and compares the results to previously published proposals.

An important problem one faces during design of a built-in self-test (BIST) based delay test is the selection of a proper generator to apply the test vectors. This problem is due to the need of applying a pair of patterns to detect any given delay fault. The second vector has to be launched against the logic immediately following the first vector. This timing requirement places severe restrictions on the kind of hardware suitable for the task, especially in built-in self-test applications where the generator must reside on chip. This paper studies the various options one has in designing the delay test vector generator. Both scan and non-scan designs are addressed. The different options are measured based on their performance, cost, and flexibility.

The paper describes a module level self-test architecture that uses weighted random patterns. A pseudorandom pattern generator (PRPG) is used to generate equally likely patterns that are then transformed to weighted patterns by a universal weighting generator. The module being tested is assumed to be composed of a number of chips all of which have been designed to support a scan test. The signature as collected by a multiple input signature register (MISR). Each scan latch in the module is fed by its near-optimal weight during test. In order to avoid any additional test pins, some of the existing signal pins are designated (demultiplexed) to perform a weight control function during test. This architecture can dramatically decrease the self-test time with only a small increase of hardware overhead.

Quite often built-in self-test (BIST) designs make use of multiple-input signature registers (MISRs) to compress the test data. Normally a MISR includes a stage for every signal that it is sampling. In some applications this leads to very wide MISRs that may include several hundred stages. Wide MISRs pose problems in terms of hardware and wiring overhead. Shorter compressors are, therefore, needed. This paper investigates the problem of shrinking a MISR so that it samples multiple signals at every stage. The ultimate shrinkage occurs when only the parity of the sampled signals is compressed. This is the case when a MISR is replaced by a single-input signature register (SISR). Issues like detection probability loss, test length penalty, fault coverage degradation, are some of the disadvantages that may arise from the MISR shrinkage. Minimizing the effect of these issues is a precondition to the success of this method.

Quite often built-in self-test (BIST) designs make use of multiple-input signature registers (MISR's) to compress the test data. Normally a MISR includes a stage for every signal that it is sampling. In some applications this leads to very wide MISR's that may include several hundred stages. Wide MISR's pose problems in terms of hardware and wiring overhead. Shorter compressors are, therefore, needed. This paper investigates the problem of shrinking an MISR so that it samples multiple signals at every stage. The ultimate shrinkage occurs when only the parity of the sampled signals is compressed. This is the case when a MISR is replaced by a single-input signature register (SISR). Issues like detection probability loss, test length penalty, and fault coverage degradation are some of the disadvantages that may arise from the MISR shrinkage. Minimizing the effect of these issues is a precondition to the success of this method.>

A broad-side delay test is a form of a scan-based delay test, where the first vector of the pair is scanned into the chain, and the second vector of the pair is the combinational circuit's response to this first vector. This delay test form is called "broad-side" since the second vector of the delay test pair is provided in a broad-side fashion, namely through the logic. This paper concentrates on generation of broad-side delay test vectors; shows the results of experiments conducted on the ISCAS sequential benchmarks, and discusses some concerns of the broad-side delay test strategy.>

A broad-side delay test is a form of a scan-based delay test, where the first vector of the pair is scanned into the chain and the second vector of the pair is the combinational circuit's response to this first vector. This delay test form is called "broad-side" since the second vector of the delay test pair is provided in a broad-side fashion, namely through the logic. This paper concentrates on several issues concerning broad-side delay test. It analyzes the effectiveness of broad-side delay test; shows how to compute broad-side delay test vectors; shows how to generate broad-side delay test vectors using existing tools that were aimed at stuck-at faults; shows how to compute the detection probability of a transition fault using broad-side pseudo-random patterns; shows the results of experiments conducted on the ISCAS sequential benchmarks; and discusses some concerns of the broad-side delay test strategy. It is shown that the broad-side method is inferior to the skewed-load method, which is another form of scan-based transition test. There is, however, a merit in combining the skewed-load method with the broad-side method. This combined method will achieve a higher transition fault coverage than each individual method alone.>

A broad-side delay test is a form of a scan-based delay test, where the first vector of the pair is scanned into the chain, and the second vector of the pair is the combinational circuit's response to this first vector. This delay test form is called "broad-side" since the second vector of the delay test pair is provided in a broad-side fashion, namely through the logic. This paper concentrates on generation of broadside delay test vectors; shows the results of experiments conducted on the ISCAS sequential benchmarks, and discusses some concerns of the broad-side delay test strategy.>

Skewed-load transition test is a form of scan-based transition test where the second vector of the delay test pair is a one bit shift over the first vector in the pair. This situation occurs when testing the combinational logic residing between scan chains. In the skewed-load test protocol, in order not to disturb the logic initialized by the first vector of the delay test pair, the second vector of the pair (the one that launches the transition) is required to be the next (i.e., one-bit-shift) pattern in the scan chain. Although a skewed-load transition test is attractive from a timing point of view, there are various problems that may arise if this strategy is used. Here, several issues of skewed-load transition test are investigated. Issues such as transition test calculus, detection probability of transition faults, transition fault coverage, and enhancement of transition test quality are thoroughly studied.>

A skewed-load transition test is a delay test where the second vector of the delay test pair is a one bit shift over the first vector in the pair. This situation occurs when testing the combinational logic residing between scan chains. This paper concentrates on the issue of coverage in skewed-load transition test. A topological lower bound of the transition test coverage is derived. This bound is shown to work well for the entire family if ISCAS combinational circuits. It is also shown that input ordering plays a key role in the attainable transition fault coverage. The paper describes a heuristic for input ordering that will achieve a nearly optimal transition fault coverage.

The author's objective is to introduce the reader to the fast emerging field of AC test for digital logic circuits. He includes a brief discussion of the important concepts, algorithms and circuits that are used in conjunction with AC test. A comprehensive bibliography is provided.>

Discusses the problem of estimating the sum of the detection probabilities of the yet unobserved faults during a random pattern test of a given digital circuit. The authors describe a statistical method for this purpose. The method requires keeping track of each fault until it is detected for the second time, and thus the simulation cost is about twice the cost of a similar simulation which abandons faults after their first detect. The benefits of having an estimate of the sum of these detection probabilities are twofold: (1) it provides a good stopping rule whenever 100% fault coverage is infeasible (which is often the case), and (2) it provides an estimate of the required effort to detect the next fault. The results of tests performed on some circuits are presented.>

The authors describe a design of an LFSR (linear feedback shift register) that can easily accommodate a change-of-seeds feature. This new LFSR is controlled by two separate clocks, one for the normal LFSR operation and one for the change of seeds option. The change of seeds is fast since it is accomplished by a pair of clock pulses rather than by long scan operations.>

In many circles at-speed test is synonymous to AC test. The object of this paper is to root out this misconception. In order to achieve an effective AC test special attention must be paid to the way the patterns are generated. The AC strength is a measure that allows assessing how well a pattern generator can serve in applying AC test vectors to the logic. Generators with high AC strengths tend to perform better than generators with low AC strengths.

Two test strategies for memory testing are compared for their ability to detect coupled-cell faults in an n-word-by-1-bit random access memory. In both strategies the data-in line is randomly driven. One of the two strategies uses random selection of both the address lines and the read/write control. The other strategy sequentially cycles through the address space with deterministic setting of the read/write control. The relative merit of the two strategies is measured by the average number of accesses per address needed to meet a standard test quality level.>

The circumstances under which a partitioning of a task with a polynomial complexity will result in an overall reduction of its execution time are analyzed. It is assumed that the task executor is sequential in nature, namely it can execute only one task at a time. Since partitioning of a task into smaller subtasks will, most probably, result in subtask overlap, there is a risk that a given partitioning scheme will yield an increase in its overall execution time. Formulas are derived to test the effectiveness of any proposed partitioning scheme. In the case of multiple partitioning options, the best one can be easily obtained. One of the possible tasks that this analysis is applicable to is the test generation of digital circuits with a uniprocessor.>

The author considers the AC defect level and yield loss after test for both logic and random-access-memory semiconductor chips. Computation of chip AC defect level and yield loss after test is dependent upon the availability of statistical information regarding the behavior of the chip's delay and of the tester error. This statistical information can either be derived from manufacturing process parameters or measured by a tester. It is shown that there is a relationship between the chip-shipped defect level and the yield loss after test. Thus, a change in one will, in general, affect the other.>

The authors describe the design of an LSSD-(level-sensitive-scan-design) based LFSR (linear feedback shift register) which is capable of changing seeds by applying a pair of clock pulses at the time of the change. This LFSR is controlled by two separate clocks, one for the normal LFSR operation and one for the change-of-seeds option. The newly generated seeds are uniformly distributed over the entire pattern space. The change of seeds is fast, since it is accomplished by a pair of clock pulses rather than by long scan operations.>

Five test strategies for memory testing are compared for their ability to detect coupled-cell faults in an n-word-by-1-b random-access memory. In all five test strategies the data-in line is randomly driven. Three of five strategies use random selection of both the address lines and the read/write control. The other two strategies sequentially cycle through the address space with deterministic setting of the read/write control. The relative merit of these five strategies is measured by the average number of accesses per address needed to meet a standard test quality level. It is concluded that ETWO (explicit memory test with word operations) offers the best performance and is quite easy to implement.>

A method is presented of operating on signatures from a cycling register such that the complexity of identifying multiple failing tests is comparable to that of identifying a single failing test. The method has some interesting aliasing characteristics. The authors show the probability of aliasing and suggest how it can be kept relatively small. The efficiency of the method decreases as the number of failing tests increase. The reduction in efficiency is due to an increase in aliasing probability caused by footprints being lost in the cycling registers. The larger the number of failing tests, the greater is the chance that aliasing will occur.>

A procedure is described for determining the initial value of a single or multiple input signature register (used to compress responses in built-in testing) so that the final good-machine signature is always constant, e.g. all zeros. In this way, it is possible to determine if a fault has been detected by ORing the outputs of the register stages. Since the OR operation can be built-in, a single observation of the output of the OR gate will determine if the circuit has passed the test.>

In a computer system, the maximum allowable propagation delay of the combinational logic networks between latches is equal to the interval between the system clocks. The objective of delay testing is to guarantee that the delay of the manufactured network falls within specifications. Here, the capability of random patterns to detect slow paths in combinational logic is analyzed. Formulas that relate the length of the test to the desired test quality are derived.>

An analytical method is described for determining the random pattern testability of permanent faults in the prelogic driving the data-in and the address lines of a multiport random access memory whose outputs are directly observable. The results can be used with minimal extensions to existing detection probability tools such as the cutting algorithm.

This paper describes a new type of shift register latch that is compatible with LSSD. The new latch has the property that information may be shifted in and out of it in two directions: left to right and right to left.

This correspondence addresses actual implementation of a multiway fan-out and its effect on test generation. If a test generation ignores the fan-out implementation faults may be left undetected by the test set. Moreover, different implementations of the multiway fan-out may lead to different fault coverages. Careless implementation of the fan-out may also yield undetectable faults. Some guidelines for fan-out implementation that may enhance testability are given in this correspondence.

The testing of large logic networks with random patterns is examined. Work by previous workers for single faults is extended to a class of multiple fault situations. Not only is the problem of fault detection in the presence of nonmasking multiple faults treated, but the question of distinguishing between them is also examined. It is shown that a test that merely exposes each fault has a high probability of distinguishing between the faults. The relationships between quality, diagnostic resolution, and random pattern test length are developed. The results have application to self-test schemes that use random patterns as stimuli.

A major problem in self testing with random inputs is verification of the test quality, i.e., the computation of the fault coverage. The brute-force approach of using full-fault simulation does not seem attractive because of the logic structure volume, and the CPU time encountered. A new approach is therefore necessary. This paper describes a new analytical method of computing the fault coverage that is fast compared with simulation. If the fault coverage falls below a certain threshold, it is possible to identify the ``random-pattern-resistant'' faults, modify the logic to make them easy to detect, and thus, increase the fault coverage of the random test.

In a number of applications, it is necessary to generate stimnuli: to generate random patterns when random testing of logic faults is employed, and to generate the random occurrence of events when simulation is used, to mention two. In this paper, we show a quick empirical test, which is based on a data compression method, to analyze the pseudorandom integers generated by certain types of random integer generators and to determine whether the approximation to a true random process is good.

In this paper we show that good controllability and observability do not guarantee good testability. In fact, one can easily find examples of faults that are difficult or impossible to detect, although both the controllability and observability figures are good.

With the advent of VLSI, testing has become one of the most costly, complicated, and time consuming problems. The method of syndrome- testing is applicable toward VLSI testing since it does not require test generation and fault simulation. It can also be considered as a vehicle for self-testing. In order to employ syndrome-testing in VLSI, we electronically partition the chip into macros in test mode. The macros are then syndrome tested in sequence.

In [1] and [2] a method of designing syndrome-testable combinational circuits was described. It was shown that, in general, syndrome-testable combinational circuits require some pin-penalty and maybe some logic for producing the testable design.

Intermittent faults in combinational circuits may appear and disappear randomly; hence, their detection requires many repeated applications of test vectors. Since testing reduces the time available for computation, it is necessary to efficiently minimize the time required for a test, while still achieving a high degree of fault detection.

Classical testing of combinational circuits requires a list of the fault-free response of the circuit to the test set. For most practical circuits implemented today the large storage requirement for such a list makes such a test procedure very expensive. Moreover, the computational cost to generate the test set increases exponentially with the circuit size.

Testing for intermittent faults in digital circuits has been given significant attention in the past few years. However, very little theoretical work was done regarding their detection in sequential circuits.