Hardware prefetchers such as SPP rely on address-delta history and perform poorly on event-driven workloads, where event-type switches invalidate recent patterns. On an HFT order-book engine, SPP achieves only 8.0% L2 prefetch accuracy with 85.9% late prefetches; on B+Tree under uniform-random access, it degrades IPC by 6.7–8.1%. We present STP (Semantic-Triggered Prefetcher), which exposes event type through one non-privileged x86 hint instruction, SETHINT imm8, and combines two lightweight mechanisms: an Event Footprint Table (EFT) that replays high-frequency missed lines at type transitions, and a PC-Localized Working Set (PLWS) that gates next-line prefetching by per-PC miss rate with asymmetric feedback throttling. In gem5 on one HFT and four B+Tree settings, STP achieves up to 10 × higher L2 prefetch accuracy with 3–10 × fewer requests (up to 90% less bandwidth). On HFT, STP improves IPC by 36.1% over NoPF and by 5.4% over SPP (0.543 vs. 0.515). Under low locality, STP limits impact to − 2.0% or +0.8%, where SPP drops 6.7–8.1%. Hardware cost is 5.4 KB, reducible to ~3.1 KB.

The increasing deployment of neural networks in safety-critical domains, such as autonomous driving and embodied artificial intelligence, has underscored the urgent need for fault-tolerant neural architectures. Hardware-induced faults stemming from soft errors, aging, or other disturbances can severely impair model performance. In this paper, we propose a hierarchical optimization framework that systematically designs fault-tolerant neural architectures from operator design to architecture search method, while minimizing both accuracy loss and computational cost. Specifically, we design a fully decoupled Winograd convolution operator (FD-WGC) that localizes the impact of bit-flip faults and reduces computational cost. We then expand the architecture search space by introducing fault-tolerant cells composed of the FD-WGC and complementary operators, enabling more flexible network construction. Within this expanded search space, we employ MOBO-NAS, a multi-objective Bayesian optimization based neural architecture search method, to efficiently explore neural architectures that balance accuracy, computational cost, and fault tolerance. Experimental results show that our framework enhances fault tolerance by up to 510× compared to state-of-the-art (SOTA) manually designed and automatically searched architectures, while maintaining comparable accuracy and reducing computational cost by up to 80%. Extensive evaluations across diverse hardware fault models further validate the generalizability and effectiveness of our proposed framework. All codes are available at https://github.com/cc-innocence/MOBO-NAS/tree/master.

In fields where fault tolerance is critical, such as aerospace and autonomous driving, the Triple Modular Redundancy (TMR) is widely utilized due to its high reliability, yet it comes with significant overhead. To mitigate this issue, Approximate TMR (ATMR) has emerged as a promising solution. However, few studies have addressed the multi-objective optimization problem between hardware saving and fault tolerance caused by approximation. This paper presents two pioneering multi-objective optimization frameworks tailored for fault-tolerant circuit design that leverage approximate redundancy to achieve this delicate balance. The first framework, Dynamic Adjustment Multi-Objective Optimization (DA-MOO), proposes a Dynamic Adjustment Optimized NSGA-II (DAON) algorithm utilizing parity expansion and dynamic probability adjustment to generate ATMR solutions. This method surpasses traditional TMR by halving area and power overhead while still achieving over 70% of fault coverage. Considering the computational intensity of DA-MOO, we further propose the Pre-Encoding Multi-Objective Bayesian Optimization (PE-MOBO) framework, achieving a 198x improvement in computational time over traditional methods. In summary, DA-MOO is well-suited for scenarios requiring a premium on reliability alongside cost-efficiency, such as in the commercial aerospace industry, while PE-MOBO is particularly advantageous for applications demanding rapid design cycles, like consumer electronics.

Blind Face Restoration (BFR) involves restoring high-quality images from various unknown and severely degraded counterparts, which is a challenging task due to the conflicting objectives of content reconstruction and detail generation. In this paper, we propose a closely-coupled approach to address this problem and achieve photorealistic and faithful reproductions. Specifically, we propose a two-step image restoration model that consists of the following steps: Firstly, we train a BaseNet that incorporates a filtered feature fusion module ($F^{3}M$) to purify degraded feature maps. Secondly, while keeping the BaseNet fixed, we train a DetailNet that utilizes a feature probabilistic model to generate high-frequency detail information. The proposed framework not only separates the reconstruction and generation processes but also deeply analyzes their interactions, leading to an optimized balance between perceptual quality and fidelity. Our approach is validated through extensive experiments on both synthetic datasets and real-world facial photographs, demonstrating significant improvements in Frechet Inception Distance (FID) scores while maintaining identity consistency. The experimental results highlight our method's state-of-the-art performance, achieving superior visual quality and processing efficiency compared to existing methods.

Dynamic vision sensors (DVSs), renowned for their low latency and sparse event-driven output, have garnered significant attention in machine vision applications, particularly in latency-sensitive applications like object tracking. However, current DVS-based object tracking systems have not fully utilized the advantages of DVS due to their frame-based processing or the high computing intensity of their algorithms. This brief presents EDMOT, a fully event-driven multiobject tracking system for DVS, achieving 25–65 ns latency at 200 MHz. EDMOT introduces three key innovations: 1) a novel event-driven update mechanism that processes only the latest event and the expired oldest event, minimizing computational overhead; 2) a dual-threshold tracking strategy that decouples object formation and motion phases, significantly improving tracking accuracy; and 3) a row–column feature memory with flag registers, enabling object separation within eight clock cycles. The proposed EDMOT is evaluated on public datasets, demonstrating superior tracking accuracy compared to prior methods. Finally, EDMOT was implemented at the HLMC 55 nm, supporting 20–100 Me/s throughput. To the best of our knowledge, this is a multiobject tracking system with minimal delay and the highest event processing throughput.

The growing demand for energy-efficient computing in resource-constrained devices necessitates approximate arithmetic solutions that balance accuracy and hardware cost. This article presents a family of logarithmic truncation-based approximate multipliers (LTAMs) for floating-point (FP) operations, including two hardware cost-optimized architectures (LTAM1and LTAM2) and an accuracy-focused lookup table (LUT)-based design (LTAM-LUT). All designs effectively address the systematic negative bias inherent in classical logarithmic multipliers through advanced error compensation methods. Based on a comprehensive analysis, a 6-bit mantissa truncation is identified as the optimal configuration. Under the 6-bit configuration, LTAM1-6achieves 52.9% area and 77.6% power-delay product (PDP) reduction compared to conventional logarithmic approximate multipliers, while LTAM2-6 provides 45.1% area and 70.4% PDP reduction. LTAM-LUT achieves 56.4% accuracy improvement over conventional logarithmic approximate multipliers with a mean relative error distance (MRED) of 1.68%, the lowest among all compared designs. These hardware efficiency gains are also validated across diverse application domains. In HDR tone mapping, LTAM-LUT achieves up to 7.0dB higher peak signal-to-noise ratio (PSNR) than conventional designs, while LTAM1-6and LTAM2-6 provide 1.1- and 4.6-dB improvements, respectively. For single-image super-resolution (SISR) on DIV2K ($\times 4$scale), LTAM-LUT preserves reconstruction quality nearly identical to exact arithmetic on HAT (29.73dB) and achieves up to 2.3dB higher PSNR than conventional logarithmic multipliers on EDSR, while LTAM1-6and LTAM2-6 consistently outperform prior approximate designs across all tested architectures, demonstrating superior accuracy–efficiency tradeoffs for error-tolerant applications.

This article presents a systematic design methodology for multi-input piezoelectric energy harvesting (PEH) using collaborative-flip synchronized switch harvesting on capacitors (CF-SSHCs). We address a fundamental scaling limitation: conventional synchronized switch harvesting on capacitor (SSHC) efficiency degrades as the number of parallel transducers increases due to rising equivalent capacitance. Starting from the theoretical foundations of a two-transducer single-stage topology, we develop closed-form expressions for the voltage flipping factor and power extraction that reveal a 7.4% maximum power improvement over conventional SSHC. Extending to multistage architectures, results show that an 8-stage configuration achieves 32.2% power enhancement through 33 collaborative-flipping phases. For generalized$M$-input$N$-stage systems, the derived analytical framework demonstrates that the maximum output power improvement ratio (MOPIR) scales from 3.8 to 9 as transducer count increases from 1 to 60 in an 8-stage implementation. We formulate an optimization algorithm for automated parameter selection and provide closed-form design equations considering practical issues, including phase asynchrony and capacitance mismatch. This work establishes a complete theoretical framework enabling systematic design of multitransducer energy harvesting interfaces rather than empirical topology exploration.

As integrated circuits (ICs) continue to scale, soft errors pose a growing threat to system reliability—particularly in safety-critical applications. Among various circuit components, flip-flops (FFs) are especially susceptible to soft errors due to their state-holding nature, making them prime targets for selective hardening. However, such hardening introduces area and power overheads, necessitating careful tradeoffs. Existing methods typically rely on multiobjective optimization (MOO) algorithms to identify Pareto-optimal hardening strategies, yet their inherent randomness limits controllability, and they must be rerun entirely for each new circuit instance, resulting in poor adaptability. In this work, we propose a deep reinforcement learning (DRL)-based hardening optimizer that supports zero-shot generalization to unseen circuits. Built upon the advantage actor–critic (A2C) framework, our model is trained on synthetic circuits and learns to make sequential hardening decisions under strict resource constraints. A recurrent neural network (RNN) captures the historical context of prior hardening steps, while an attention mechanism dynamically focuses on FFs with high soft-error vulnerability at each decision step. Experimental evaluations on benchmark circuits demonstrate that our proposed framework achieves an average hypervolume (HV) improvement of 19.58%. Furthermore, the framework provides at least a$9.9\times $runtime speedup for individual circuits, offering an agile and generalizable solution for reliability-centric circuit design. The source code is available athttps://github.com/Magic00JuJu/ZACHO/tree/main

The rapid growth of model sizes in advanced artificial intelligence algorithms, particularly in Transformerbased large language models (LLMs), has led to significant computational overhead. Mixture-of-Expert (MoE) models offer a solution through their sparsely gating mechanism but introduce new challenges of extensive all-to-all communication and model computational inefficiencies. This paper presents Hydra, a software/hardware co-design aimed at accelerating MoE inference on chiplet-based architectures. In software, Hydra employs a popularity-aware expert mapping strategy to optimize interchiplet communication. In hardware, it incorporates Content Addressable Memory (CAM) to eliminate expensive explicit token (un)-permutation based on sparse matrix multiplications and a redundant-calculation-skipping softmax engine to bypass unnecessary division and exponential operations. Evaluated in 22 nm technology, Hydra achieves latency reductions of $14.2 \times$ and $3.5 \times$ and power reductions of $169.1 \times$ and $18.9 \times$ over GPU and state-of-the-art MoE accelerator, respectively, thereby offering a scalable and efficient solution for MoE model deployment.

Mixture-of-experts (MoE) technique holds significant promise for scaling up Transformer models. However, the data transfer overhead and imbalanced workload hinder efficient deployment. This work presents PIMoE, a heterogeneous system combining processing-in-memory (PIM) and neural-processing-unit (NPU) to facilitate efficient MoE Transformer inference. We propose a throttle-aware task offloading method that addresses workload imbalance between NPU and PIM, achieving optimal task distribution. Furthermore, we design a near-memory-controller data condenser to address the mismatch of sparse data layout between NPU and PIM, enhancing data transfer efficiency. Experimental results demonstrate that PIMoE achieves $4.5 \times$ speedup and $13.7 \times$ greater energy efficiency compared to the A 100, and $1.4 \times$ speedup over a state-of-the-art MoE platform.

Asymmetric Numeral Systems (ANS) play a significant role in learned image codecs (LIC) because of their high coding efficiency. However, it constitutes a substantial portion of inference time, making it the main bottleneck in real-time LIC due to its high computational demands, complex control logic, and serial execution flow. To address these challenges, this paper introduces a hardware-oriented ANS algorithm hANS that reduces complex calculations for state encoding and state-symbol decoding. Furthermore, hANS employs fixed-latency calculation to eliminate control logic, which often causes inconsistent delays. To further enhance throughput, we propose a hardware architecture of ANS for LIC (ANS-LIC), introducing a novel hardware parallelism scheme that incorporates pipeline execution and multi-bin parallelism for encoding, along with multi-stream parallelism for decoding. Additionally, by optimizing the execution order, we achieve a reduction in hardware resource utilization during the decoding process. The proposed ANS-LIC hardware is implemented in RTL and synthesized using TSMC 65nm technology and the Alveo U250 Data Center Accelerator Card. We evaluate ANS-LIC on the Kodak and DIV2K LIC datasets, achieving a 1.17% compression ratio improvement over the SOTA method, Recoil. The implementation results and comparison with other works are presented in Table 1. The synthesis indicates that ANS-LIC requires only 385.5/393.0k gates for encoding and decoding, without SRAM. ANS-LIC achieves throughput improvements of 13.29×/1.47× for encoding and decoding over Recoil. In summary, the proposed ANS-LIC demonstrates substantial advantages.

In the era of big data, the demand for memory capacity in modern computing systems is surging. The CXL-SSD, NAND Flash-based memory expander using emerging Compute Express Link (CXL), has become a promising solution for efficient memory expansion. However, the memory-expansion scenario poses severe performance and endurance challenges for CXL-SSDs, and existing works fail to fully address them due to the usage of traditional SSDs as back-end media. To optimize these aspects, we propose LsCMM-H, a Total-Cost-of-Ownership (TCO) -efficient CXL-SSD architecture with Zoned Namespace (ZNS) SSDs as back-end media for better latency and lifetime. LsCMM-H employs hardware-software co-designed log management, low-overhead data-tiering-based garbage collection mechanism, and read acceleration to leverage the benefits of ZNS. Based on our evaluation, LsCMM-H reduces tail latency by 49.9%, improves throughput by 41.9%, endurance by 280.5%, and saves TCO by 72.4% compared to vanilla CXL-SSD. The additional comparison also demonstrates the superiority of our proposed log structure.

3D Gaussian Splatting (3DGS)–based rendering has gained increasing attention due to its state-of-the-art quality and broad applications in Augmented and Virtual Reality (AR/VR). However, the deployment of 3DGS in edge systems (~10FPS) faces challenge in achieving real-time (≥30FPS) performance due to computational resource constraints. Profiling reveals that the Gauss-Tile rasterization critically impacts pipeline efficiency due to its decoupled nature and computation-accuracy trade-off, which current hardware devices cannot effectively resolve. To this end, we propose a software-hardware co-design that performs rasterization via pattern matching. Our solution adopts flood encoding to represent tile coverage efficiently. It integrates a pattern-aware rasterization unit (PRU) and compresses the codebook using k-means clustering, preserving accuracy with minimal area overhead. At the architectural level, GauPRE adopts early depth-sorting and tile-group-wise rasterization to fuse coverage testing and alpha blending, enabling seamless data flow. We further integrated GauPRE with the GPU to support the end-to-end 3DGS rendering pipeline. Results demonstrate that the GPU+GauPRE delivers an 11.6× end-to-end speedup over the Jetson Orin Nano with only 0.1% area overhead. Meanwhile, the standalone GauPRE rasterization engine achieves 2.09× higher throughput compared to a state-of-the-art 3DGS accelerator.

SRAM suffers from single event upset (SEU) and single event transient (SET) in harsh radiation environments. In this paper, a Penta Interlocking Dual Ports 14T (PIDP-14T) SRAM cell is proposed to improve cell stability. The PIDP-14T has the immunity of single node upset (SNU), multiple node upsets (MNU) and specific triple node upset (TNU). An inside-bit interleaving layout isolation method increases the distance of nearest sensitive nodes to 2.409 µm. Additionally, as SET in peripheral circuit results in half-select disturbance during the operation cycle, this paper introduced double module redundant (DMR) hardened decoding circuit to remove SET. The simulation results show that the cell can recover from special MNU of which the critical charge is almost 4 times of other cells, and the dual gate cell with DMR hardened decoding array are robust to write disturbance caused by SET.

Abstract Rice is a widely cultivated crop in Asia and is paramount in ensuring national and global food security. However, rice plants are susceptible to various diseases that negatively impact crop quality and quantity to meet the needs of the world’s growing population. Automated rice plant disease classification ensures food security and agricultural sustainability. Although traditional deep learning approaches have shown promising results in rice plant disease classification, the challenges posed by the heterogeneity of the data set and the feature imbalance persist. This research introduces a robust and novel Ensemble Attention Mechanism (EAM) that uses fine-tuning transfer learning to address these challenges and pre-trained (VGG16, VGG19, and customized ResNet called RiceNet, which comprises ResNet18 and ResNet50) as baseline models, specifically tailored to improve rice plant disease classification within heterogeneous datasets. The main contribution of this paper is to introduce a RiceNet framework that incorporates ensemble learning principles and attention mechanisms to adaptively balance data heterogeneity and feature representation by effectively integrating every representation to mitigate inherent class distribution imbalances. Comprehensive ablation studies validate the effectiveness of each component in the framework, demonstrating significant improvements in classification performance compared to traditional methods. Furthermore, the evaluation of RiceNet on two extensive publicly available datasets (close environment and field environment) shows its superior performance, achieving an impressive F1 score of 100% and a balanced precision of 100% on both large and small datasets. This research sets a new benchmark for rice disease classification and provides a versatile framework applicable to agricultural precision, contributing to food security and sustainability.

The Versatile Video Coding (VVC) standard notably enhances encoding efficiency with the Quad-Tree plus Multi-Type Tree (QTMTT) partition structure. However, the complex QTMTT tool presents substantial challenges in both software and hardware implementation. To overcome those challenges, this paper introduces a hardware-friendly partition decision algorithm for VVC intra and inter coding. Firstly, we propose a lightweight backbone network to extract partition-aware features. Secondly, we employ a Quantisation Parameter (QP) fusion network to regulate the impact of QPs on the partition structure. Additionally, we apply a top-down threshold-driven post-processing algorithm, in which improbable partition types are removed to directly derive the unique partition structure. Experiments show that our method not only exceeds the previous state-of-the-art work in BD-BR performance, but also shows sufficient hardware-friendly characteristics. To the best of our knowledge, this work is among the earliest to comprehensively discuss and implement a hardware-friendly partition decision algorithm.

Graph Attention Network (GAT) has gained widespread adoption thanks to its exceptional performance in processing non-Euclidean graphs. The critical components of a GAT model involve aggregation and attention, which cause numerous main-memory access, occupying significant inference time. Recently, much research has proposed near-memory processing (NMP) architectures to accelerate aggregation. However, graph attention requires additional operations distinct from aggregation, making previous NMP architectures less suitable for supporting GAT, as they typically target aggregation-only workloads. In this paper, we propose GATe, a practical and efficientGATaccelerator with NMP architecture. To the best of our knowledge, this is the first time that accelerates both attention and aggregation computation on DIMM. We unify feature vector access to eliminate the two repetitive memory accesses to source nodes caused by the sequential phase-by-phase execution of attention and aggregation. Next, we refine the computation flow to reduce data dependencies in concatenation and softmax, which lowers on-chip memory usage and communication overhead. Additionally, we introduce a novel sharding method that enhances data reusability of high-degree nodes. Experiments show that GATe achieves substantial speedup of GAT attention and aggregation phases up to 6.77× and 2.46×, with average to 3.69× and 2.24×, respectively, compared to state-of-the-art NMP works GNNear and GraNDe.

Neuromorphic computing has emerged as a revolutionary technology in consumer electronics, with computing-in-memory (CIM) attracting considerable attention for its potential to minimize data transfer. However, most CIM accelerators necessitate numerous digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) for mixed-signal data processing, resulting in substantial area and energy overheads. This study introduces a lightweight CIM accelerator, Light-CIM, which operates with fully analog tiles (FANTs) and employs a nonideality-aware algorithm. A FANT consists of one-transistor-one-resistor (1T1R) arrays based on resistive random access memory (RRAM) and customized analog peripheral circuits for data processing. The intratile data computation, transfer, and buffering are all in analog voltage, current, or RRAM resistance, thus eliminating costly DACs and ADCs for intermediate data conversions in conventional CIM accelerators. The fully analog approach significantly reduces power consumption attributed to ADCs, accounting for only 2.5% of the total power consumption. Additionally, a nonideality-aware training algorithm is employed to enhance the robustness of the hardware system. It models and incorporates nonidealities of circuits in software training, including read nonlinearities, mismatches, variations, and noises in the hardware analog data flow. Experimental results demonstrate that Light-CIM achieves accuracy close to software performance in various NN models. Light-CIM accomplishes a compute density of 3.91 TOPS/${\mathrm { mm}}^{2}$and an energy efficiency of 3.08 TOPS/W, both highly competitive compared to state-of-the-art works.

This paper proposed an algorithm-hardware co-design of an event-driven spiking neural network (SNN) accelerator for classification tasks of event-based data from dynamic vision sensors (DVS), which can implement a feed-forward SNN with a maximum network size of 1 million synapses. Configurable structured sparsity is introduced between the first layer and the second layer to improve energy efficiency and balance the workload between different processing elements (PEs). The number of available neurons in the accelerator is sparsity-dependent and ranges from 1024 to 4096. The modified leaky-integrate-fire (LIF) neuron model and an event-driven neuron update scheme are employed in both algorithm and hardware to fully utilize the natural sparsity of DVS event stream. Early-stop inference strategy on the hardware enables a trade-off between inference accuracy and efficiency. A three-layer fully connected SNN is trained through backpropagation through time (BPTT) and is implemented and evaluated on Xilinx ZCU104 FPGA. Our design can achieve 96.0% accuracy on the N-MNIST dataset and 79.0% accuracy on the DVS128-Gesture dataset both at 50% sparsity. The top performance of the accelerator on ZCU104 is 3.22 GSOP/S and 3.99 GSOP/W at 250 MHz.

Computing-in-memory (CIM) based on embedded nonvolatile memory (NVM) realizes energy-efficient acceleration of convolution neural network (CNN) with less data movement and high computing parallelism. Because the deployment environments for edge devices are usually subject to changes, it is necessary for the CIM accelerators to support light-weight on-chip training with efficient implementation for environmental adaptation. However, previous CIM accelerators for edge devices mainly realize the inference while the training is performed on cloud. The limited endurance of NVMs hinders the CIM accelerators from supporting on-chip training that involves a large number of weight updates. In this paper, an endurance friendly CIM accelerator based on NVM, EF-CIM, is presented with bit-aware wear-leveling for efficient on-chip training in edge devices. Firstly, the bit split weight mapping (BSWM) splits the multi-bit weights into individual bits and stores them in the array alternately. Then, the bit-aware wear-leveling (BAWL) reduces the NVM updates by using verify write and block switch methods. An EF-CIM accelerator with BSWM and BAWL that is evaluated for 8-bit inputs and weights in the 28nm process achieves ~3.58/3.26 TOPS/W energy efficiency for feed-forward/ back-propagation, 5X lower computing latency. The BAWL also alleviates the wear of NVMs by 40X, achieving high NVM training reliability.

This paper presents an all-NMOS RF-DC rectifier with internal$V_{\mathrm {TH}}$cancellation (IVC) technique to achieve an ultra-wide high-PCE input power range for RF energy harvesting. The all-NMOS topology replaces the PMOS transistor in the conventional cross-coupled rectifier with a diode-like NMOS transistor to obtain the maximum current driving capability while effectively reducing the reverse leakage current at higher input power, combining the strengths of diode-based and cross-coupled rectifiers. The IVC unit is used to compensate for the threshold voltage of the diode-like rectifying transistor on the output side and improve the PCE at low input power. As a result, the sensitivity and the input power range are improved simultaneously. The proposed rectifier is fabricated with a 0.18-$\mu $m standard CMOS technology. The measurement results show that the IVC all-NMOS rectifier achieves 55% PCE, −15.5 dBm sensitivity and 18.6 dB input power range when operating at 900 MHz with a 30 k$\Omega $load.

Simultaneous Localization and Mapping (SLAM) is pivotal for autonomous robotics, yet feature-based SLAM systems struggle with sparse environmental representations and robustness under dynamic conditions. Optical-flow-based SLAM (OpF-SLAM) addresses these limitations by leveraging pixel-level motion data for dense mapping; however, its computational intensity hinders real-time deployment. This paper presents RT-FLOW, an FPGA-based accelerator for OpF-SLAM that achieves real-time performance through three key innovations: 1) A feature-context encoding engine that exploits inter-frame similarity to resolve data dependency in correlation construction, reducing latency by 77.5%. 2) A heterogeneous mixed-precision flow update engine guided by correlation sparsity, enabling 3.7× faster optical flow computation with negligible accuracy loss. 3) A pivoting-free linear solver using Householder transformations for stable pose optimization. Implemented on Xilinx XCZU7EV FPGA, RT-FLOW processes full-image pixels per frame at 65 fps with an energy efficiency of 0.358 μJ/point, outperforming previous FPGA designs. Evaluated on benchmark datasets, RT-FLOW demonstrates robustness in diverse environments while maintaining sub-110mJ/frame energy consumption. This work bridges the gap between algorithmic potential and hardware feasibility for high-density SLAM, empowering next-generation mobile robots with real-time scene understanding capabilities.

ReRAM has emerged as a promising candidate for computing-in-memory due to its excellent compatibility with advanced CMOS processes, high density, and non-volatility. Meanwhile, Digital Computing-in-Memory (DCIM) offers higher energy efficiency than its analog counterpart and supports full-precision processing. However, existing ReRAM-based DCIMs are hindered by error-prone readout and low input parallelism. The inefficient bit-width reconfiguration also incurs significant hardware overhead during neural network mapping. This paper reports a 64Kb DCIM engine based on 1T2R ReRAM bitcells for multiply-and-Accumulate(MAC) acceleration. The ternary-input Booth-assisted multiply-in-memory (TB-MIM) flow allows bi-state ReRAM with limited readout margin to achieve high-accuracy computation with high parallelism. The corresponding reconfigurable vector adder-tree and accumulator (ReV-A2) effectively facilitate practical hybrid-precision network mapping. Simulations show that the proposed DCIM engine achieves a normalized throughput rate of 284.44 GOPS/Kb and an energy efficiency of 730.16 TOPS/W, surpassing previous ReRAM-based DCIM designs by$3.3\times $.

In recent years, Ising machines have emerged as a promising hardware solution for tackling combinatorial optimization problems (COPs). However, existing Ising solvers, whether based on discrete-time or continuous-time approaches, often face challenges in balancing solution quality, scalability, and computational speed. Discrete-time solvers typically suffer from slow convergence due to the sequential nature of spin updates, while continuous-time solvers often lack effective annealing mechanisms, limiting their solution accuracy. To address these limitations, this work proposes a novel architecture that integrates a differential Resistive Random Access Memory (RRAM) cell-based Ising design with a Randomized Granular Update (RAGU) method. This approach enhances scalability to larger spin systems while maintaining robust performance against circuit non-idealities and device variations. Additionally, an adaptive bitline (BL) voltage clamper is incorporated into the read path to limit current magnitudes, significantly improving power efficiency. A key feature of the RAGU method is its ability to naturally introduce randomness during the update process through coarse-grained updates, serving as an imprecise but effective sampling mechanism. This innovation not only accelerates convergence and improves the system’s ability to escape local minima but also ensures high solution quality. Extensive simulations and experiments on randomly weighted graphs with varying densities demonstrate that the proposed architecture consistently achieves near-optimal solutions ($>$96%) while drastically reducing the time-to-solution to as low as 0.6$\mu$s.

The defective pixel corrector is an essential component of the image processor, which detects and corrects defective pixels in the image. Processing discrete defective pixels that exist in the output of area-scan image sensors is the focus of current research. However, the case of defective columns produced by line scan image sensors is a massive challenge for existing algorithms. In this paper, we develop novel algorithms for the detection and correction of columnar defective pixels by modeling the properties of defective columns in the output images of line scan image sensors. In addition, we design the non-extremum verdict and texture adaptive correction for clustered defective pixels in the area scan sensors and apply them to current algorithms to get enhancement, and new algorithms are obtained. Moreover, we propose a generalized hardware architecture for detection and correction. In the experimental stage, the proposed methods are compared with the state-of-the-art methods, both at the algorithmic level and in hardware implementation. The experimental results show that, compared to the current widely used algorithms, our methods for line-scan image sensors improve the detection rate by 28%, the detection precision by 90%, and the image restoration quality by 35% with a 10% increase in hardware consumption. For area-scan image sensors, the proposed non-extremum verdict improves the detection rate by 25%, improves the precision from 0.056 to 0.983, and the texture adaptive correction mitigates the image blurring caused by the correction process, with a 37% improvement in image quality, while incurring only a 1% increase in hardware overhead. In addition, our proposed algorithms achieve comparable detection and correction results with far fewer computational and storage resource requirements than machine learning-based algorithms.

Versatile Video Coding (VVC) employs Affine Motion Compensation (AMC) to process scenes with high-order motion. To improve AMC efficiency, the Affine Motion Estimation (AME) process based on the gradient-based iterative algorithm (GIA) and block match algorithm (BMA) is introduced to the VVC Test Model (VTM). However, the AME process is highly complex and difficult for hardware implementation in real-time applications. In this context, this paper proposes a hardware-friendly AME algorithm and implements the corresponding accelerator. Firstly, the weighted least squares regression is used to reduce the iteration of GIA. Then an iteration-free search scheme is proposed to remove the search dependence during the GIA and BMA process. In addition, a motion vector clamping mechanism and four-level memory organization are proposed to solve the problem of reference pixel reading conflict, which reduces 51.7% and 67.5% internal bandwidth of the AME accelerator. Compared with the default AME process of VTM 16.0, experimental results show that the proposed algorithm reduces AME run time by 81.63% while the corresponding Bjontegaard Delta Bit Rate (BDBR) loss is only 0.492%. The proposed AME accelerator can flexibly support AME search tasks in various configurations. Synthesized with the TSMC 28nm process, the proposed architecture has a gate count of 1313K and a power consumption of 156.83 mW. It can achieve$7680\times [email protected]~30fps and the corresponding BDBR loss is 0.492%~1.835%.

Personalized recommendation systems are massively deployed in production data centers. The memory-intensive embedding layers of recommendation systems are the crucial performance bottleneck, with operations manifesting as sparse memory lookups and simple reduction computations. Recent studies propose near-memory processing (NMP) architectures to speed up embedding operations by utilizing high internal memory bandwidth. However, these solutions typically employ a fixed vector partitioning strategy that fail to adapt to changes in data center deployment scenarios and lack practicality. We propose Flips, aflexiblepartitioningstrategy NMP architecture that accelerates embedding layers. Flips supports more than ten partitioning strategies through hardware-software co-design. Novel hardware architectures and address mapping schemes are designed for the memory-side and host-side. We provide two approaches to determine the optimal partitioning strategy for each embedding table, enabling the architecture to accommodate changes in deployment scenarios. Importantly, Flips is decoupled from the NMP level and can utilize rank-level, bank-group-level and bank-level parallelism. In peer-level NMP evaluations, Flips outperforms state-of-the-art NMP solutions, RecNMP, TRiM, and ReCross by up to 4.0×, 4.1×, and 3.5×, respectively.

Versatile video coding (VVC) introduces multi-type tree (MTT) and larger coding tree unit (CTU) to improve compression efficiency compared to its predecessor High Efficiency Video Coding (HEVC). This leads to higher throughput for fractional motion estimation (FME) to meet the needs of real-time processing. In this context, this article proposes an interpolation-free algorithm based on an error surface to improve the throughput of FME hardware. The error surface is constructed by the rate-distortion costs (RDCs) of the integer motion vector (IMV) and its neighbors. To improve the prediction accuracy, a hardware-friendly RDC estimation strategy is proposed to construct the error surface. The experimental results show that the corresponding Bjontegaard Delta Bit Rate (BDBR) in Random Access (RA), Low Delay P (LDP) and Low Delay B (LDB) configuration increases by only 0.358%, 0.479%, and 0.511% compared with the VVC test model (VTM) 16.0. Compared with the default FME algorithms of VVC, the time cost of FME is reduced by 53.47%, 56.28%, and 54.23%, respectively, in RA, LDP, and LDB configurations. The algorithm is free of iteration and interpolation, which can contribute to low-cost and high-throughput hardware. The proposed architecture can support FME of all coding units (CUs) in a CTU with one layer of MTT under the quaternary tree (QT), and the CU size can vary from$8\times 8$to$128\times 128$. Synthesized using GF 28-nm process, the architecture can achieve$7680\times 4320$@60 fps throughput at 800 MHz, with a gate count of 244 K and power consumption of 76.5 mW. This proposed architecture can meet the real-time coding requirements of VVC.

This brief designs and implements a 4-D imaging light detection and ranging (LiDAR) receiver. It employs a reconfigurable transimpedance amplifier (TIA) that alternates between two modes to separately achieve ranging and light intensity quantification functions. A new mode-switching method based on a monostable multivibrator is proposed, allowing the TIA to automatically switch modes during measurement. The reconfigurable TIA and mode-switching method enable the application of charge sampling in 4-D LiDAR imaging receiver, resulting in a higher signal-to-noise ratio (SNR) compared with traditional designs. In addition, the TIA mode used for distance measurement achieves a bandwidth of 140 MHz, a gain of$99.8~\text {dB}\Omega $, and an input-referred noise of ~20-nA rms, indicating high detection sensitivity. A prototype implemented in 0.18-um CMOS verifies the feasibility of the proposed receiver, consuming 24.5 mW. Measurement results demonstrate that the prototype can effectively acquire distance and light intensity information of target objects within a range of 5 m.

Computing-in-memory (CIM) is a promising technique for hardware acceleration of neural networks (NNs) with high performance and efficiency. However, conventional dense mapping scheme cannot well support the compression and optimization of irregular sparse NNs. In this paper, we propose a heuristic and greedy weight remapping scheme for irregular sparse neural networks implemented on CIM accelerator in edge AI applications. The genetic algorithm (GA) is proposed for the first time to be utilized in the column shuffle for sparse weight remapping. Combined with the granularity exploration of the CIM, the proportion of the compressible all-zero rows increase remarkably. A greedy algorithm is then employed to planarize the unevenly compressed units, thus to improve the storage utilization of the crossbar. For hardware optimization, the pipeline is customized with a zero-skipping circuit to leverage the bit-level activation sparsity at runtime. Our results show that the proposed remapping scheme achieves 70%-94% utilization rate of the sparsity, and an average of $1.3 \times$ increment compared with the naive compression. The cooptimized CIM achieves $3-7.6 \times$ speedup and $2.1- 4.8 \times$ energy efficiency, compared with the baseline for dense NNs.

Digital Compute-in-Memory (DCIM) architectures are playing an increasingly vital role in artificial intelligence (AI) applications due to their significant energy efficiency enhancement. Coupling memory and computing logic in DCIM requires extensive customization of custom cells and layouts, thus increasing design complexity and implementation effort. To adapt to the swiftly evolving AI algorithms, DCIM compiler for agile customization is required. Previous DCIM compilers accelerate the customization process but only focus on integer computation. Moreover, with technology node scaling down, design-for-test circuits are critical for robust chip design, while previous built-in-self-test (BIST) schemes for traditional memory fail to offer support for DCIM. This paper presents ARCTIC, an agile and robust DCIM compiler supporting parameterized integer/floating-point formats with corresponding BIST circuits. To support variable precision formats (including integer and floating-point), ARCTIC applies adaptive topology and layout optimization schemes for optimal performance. The compiler is also equipped with DCIM-friendly MarchCIM BIST circuits for efficient post-silicon tests with negligible area overhead. The energy efficiency of the generated DCIM macros remains competent with the state-of-the-art counterparts.

This paper proposed a hardware-algorithm co-design of an event-driven Spiking Neural Network (SNN) accelerator with structured sparsity for Dynamic Vision Sensors (DVS) applications. The accelerator can accommodate up to 1024 neurons and 1 million synapses for a feed-forward fully connected SNN implementation. Configurable structured sparsity is introduced by modular arithmetic both in the algorithm and hardware to improve the energy efficiency, reduce the memory requirement, and balance the workload between different processing elements. With an event-driven neuron update scheme, the accelerator can fully utilize the benefits of structured sparsity and can directly process DVS output data for classification tasks without encoding. A three-layer SNN is trained through backpropagation through time (BPTT) and is implemented on Xilinx ZCU104 FPGA, which achieves 96% accuracy on the N-MNIST dataset and 79% accuracy on the DVS-Gesture dataset both at 50% sparsity. The top performance of the accelerator on ZCU104 is 3.82 GSOP/S and 5.31 GSOP/W at 250 MHz.

Nowadays, with the increase resolution of Dynamic Vision Sensor (DVS), efficient compression algorithm for event stream is needed urgently. Conventional DVS system encodes event data in address event representation (AER) for output while ignores the data redundancy imposed by the correlation of events. To address this challenge, this paper first analyzes the spatiotemporal characteristics of event stream and the impact of readout circuits. Based on the analysis, the context-based encoding strategies for spatial address, timestamp and polarity of events are proposed respectively with the consideration of data flow in DVS hardware. Besides, the hardware architecture with high parallelism is presented to implement the compression algorithm, which achieves high throughput at an affordable cost. The hardware is implemented in the 55nm process as part of a 512x512 resolution DVS. The experimental results demonstrate that our methods achieves higher average compression ratio compared to conventional and DVS-specific coding algorithms.

The dataset for Video Coding for Machines (VCM) contains sensitive information that requires privacy preservation to address vulnerabilities. Achieving a balance to protect this sensitive data while maintaining VCM performance is crucial. We introduce an autoencoder integrated with a deep learning network that utilizes the ResNet architecture. This design blurs private details while preserving the contours, offering a high-dimensional representation that upholds privacy and VCM performance. The division position between the encoder and decoder is critical, influencing the equilibrium between compression efficacy and machine task performance. We craft a flexible, position-adjustable setting for the autoencoder to optimize this, facilitating a harmonious trade-off between bitrate and mAP across various deep-learning networks. This adaptation demonstrates superior performance relative to existing models. With FasterRCNN, our methods achieve 62.3 of mAP and 5681.29 of bitrate, and their versatility is further validated using YoloV5 and SSD.

Both Versatile Video Coding (VVC) and High Efficiency Video Coding (HEVC) introduce Group of Pictures (GOP) based temporal filter (GBTF) as a pre-filter to improve compression performance. While numerous efforts have been made to optimize GBTF, there is a limited amount of research that explicitly addresses why GBTF could improve compression performance. Additionally, most optimizations have focused on the design of the filter itself, rather than on how to better integrate it with other encoding tools. In this paper, we analyze the reasons behind the superior compression performance of GBTF. Subsequently, we introduce a Coding Tree Unit (CTU)-level adaptive quantization parameter allocation method joint with GBTF to further enhance compression performance for video coding. The experimental results demonstrate that, for VVC, our method provides Bjontegaard delta bit rate (BD-BR) savings of 2.0% for Peak Signal-to-Noise Ratio (PSNR) and 4.0% for Structural Similarity index (SSIM). Furthermore, for HEVC, our method provides BD-BR savings of 3.5% for PSNR and 7.6% for SSIM.

This paper presents a 6.78MHz reconfigurable four-phase dual-output series resonant rectifier that integrates hysteresis control and the triple-mode double-frequency current wave modulation (DFCWM) technique. The rectifier accomplishes AC-DC rectification and dual-output voltage regulation within a single power stage, achieving high efficiency and a reduced number of off-chip components. The combination of hysteresis control with the triple-mode DFCWM enables rectification and voltage regulation without crossover adjustments through four independent phases. Without altering the external LC resonant frequency, more uniform power conversion and reduced output voltage ripple are achieved, while also enhancing the transient response speed of the load. When simulating with a 0.18-μm CMOS process, the dual-output voltages can be adjusted to 1.1V and 2.2V, reaching a maximum output power of 0.7W with a peak power conversion efficiency (PCE) of 89.2%. Furthermore, a rapid transient load response can be observed when the load current varies between 20mA and 200mA.

The growing demand for high-precision neural network training and inference has driven the necessity for floating-point (FP) compute-in-memory (CIM) architectures. However, compared to the extensively studied INT-CIM, the energy efficiency of FP-CIM still requires further optimization and enhancement. This work presents an energy-efficient multiply-less digital SRAM-based FP-CIM architecture. Specifically, to improve the energy efficiency and minimize the area requirement, we propose to employ logarithmic approximate FP multiplication (LAM) within the FP-CIM architecture. The LAM approximates FP multiplication by converting it into a straightforward addition operation, thereby reducing the power consumption and area. Additionally, we propose an approximate adder with error-reduced compensation to address critical path delay issues associated with carry propagation, further minimizing power consumption and area overhead. A 24Kb SRAM CIM macro with the proposed techniques is designed in a 28nm CMOS technology and occupies an area of 0.033 mm2. The simulation results show that our work achieves an energy efficiency of 19.7 TFLOPS/W with bfloat16 representation at 0.9V and 200MHz.

Frequency offset estimate (FOE) is utilized to correct the incremental phase deviation caused by transceiver local oscillator mismatches, and determine the performance of the successive carrier offset compensation module. The FFT-based FOE method offers stability and controlled precision. However, as the FFT scale increases, the algorithm’s complexity also rises, which hinders real-time implementation of high-precision FOE hardware. While several research efforts aim to simplify the algorithm, there is limited focus on hardware implementation. In this paper, we introduce a semi-folded 256-point FFT with 64-way parallelism. By reusing the 64-point FFT module, computations are completed within four clock cycles, resulting in circuit area and power savings. We further leverage the semi-folded FFT structure to implement the FOE circuit. The experiments demonstrate that under the 28nm process technology, the semi-folded FFT achieves an area efficiency of 0.0043/(mm2/GS) and a power efficiency of 2.44mW/GS when working at a frequency of 714MHz. Additionally, when working at 500MHz the semi-foleded based FOE circuit has an area of 0.787mm2and a power consumption of 319.1mW, meets the requirements of a 256Gbps 16QAM communication system.

The beamforming technique has been widely used to improve the link budget in wireless communications. Compared with the digital beamformer, the analog beamformer has much lower hardware complexity and is more suitable for low-cost mobile applications. In this paper, we consider element-level phase and gain control of the analog beamformer using two phase shifters only. By setting the phase shifts properly, simultaneous 360◦phase and 6-dB gain control (SPGC) can be achieved to form the beam pattern. We first propose a low-complexity SPGC method tailored for massive multiple-input multiple-output (MIMO). Based on the conventional and proposed SPGC methods, we then design the full-featured accelerator (FFA) and the hardware-efficient accelerator (HEA) to accelerate the computing process. These two accelerators are implemented in 28 nm technology. FFA integrates 137 kilogate equivalents (kGE) in a core area of 0.0693 mm2and dissipates 104.4 mw at 2.0 GHz with 16 degrees of parallelism, while HEA can reduce the core area by 44.6% and power consumption by 42.7% without significant performance loss.

3D Gaussian Splatting (3DGS) has recently emerged as a promising technique in the realms of 3D vision and robotics. Its capacity for rapid rendering and high-fidelity reconstruction makes it an attractive candidate for integration into Simultaneous Localization and Mapping (SLAM) systems. However, existing 3DGS-based SLAM systems still suffer from inadequate tracking throughput due to tremendous recursion in volume rendering and irregular memory access for gradient backpropagation. To address these challenges, this paper proposes GauSPU, an algorithm-hardware co-designed accelerator for supporting real-time 3DGS-based SLAM. On the algorithm side, we present a sparse-tile-sampling (STS) method for efficient pose tracking. The STS focuses on informative image regions, discarding the rest to alleviate computational workload while maintaining accuracy. At the hardware level, we make twofold efforts. Firstly, we design a sparsity-adaptive ray recursion unit (SA-RRU) to accelerate volume rendering by leveraging irregular spatial sparsity. The SA-RRU introduces a sub-tile-wise execution pattern and a Morton-based thread allocation scheme to optimize sparsity utilization. Additionally, a sparsity-aware task dispatcher ensures efficient fine-grained task scheduling. Secondly, we propose a memory-access-relaxed backpropagation engine (MAR-BE) for efficient gradient aggregation. It comprises a gradient buffer unit (GBU) for coalescing partial gradients and a pose backward unit (PBU) for pipeline-fused backpropagation, collaboratively eliminating the costly atomic operations. Sufficient experiments demonstrate that, through the integration of GauSPU and GPU, the system achieves a throughput of 33.6 FPS for real-time pose tracking in 3DGS-SLAM, presenting a significant$63.9\times$improvement in energy efficiency compared to the RTX3090 baseline.

This article proposes a multimode neuromorphic event-frame integrated vision sensor that enables event detection (ED) with simultaneous brightness measurement based on the pulse width modulation mechanism. The logarithmic voltage is directly taken as intensity information. Brightness measurement involves in-pixel voltage-to-pulse conversion and out-pixel pulse coding. The maximum event bandwidth is improved to 366 Meps by pipelining the time-prior arbiter along with the address-events grouping circuit. A wide intensity dynamic range of 105 dB can theoretically be achieved through logarithmic photoelectric conversion and pulse coding. Our sensor supports a$128\times 64$frame-like image with an improved signal-to-noise ratio of 49 dB. The experimental results indicate that the log sensitivity of the optimized logarithmic photoreceptor was measured as 164 mV/dec. The equivalent frame rate for both event and intensity reaches kilo fps, making it a promising candidate in high-speed wireless sensing applications.

Computer architecture simulators are widely used to explore new architectures, e.g., the gem5 simulator. However, gem5 has significant performance errors that may lead to misleading research results. Researchers typically reduce errors with the target machine by manual calibration methods, which are time-consuming and require significant expertise. This paper presents gem5Tune, a parameter auto-tuning framework for the gem5 simulator to reduce errors. Applying black-box optimization (BBO) methods, recommended for TPE-based Bayesian optimization, gem5Tune minimizes the error between gem5 and the target machine within a limited number of iterations. Three optimization methods, instruction calibration, sensitivity analysis, and dynamic pruning, are proposed to accelerate the error convergence. Experimental results show that compared to the manual calibration method, gem5Tune significantly reduces performance errors between gem5 and three modern ARM servers by more than 10% (13.83%, 10.86%, and 25.22%, respectively) for SPEC CPU benchmarks. It also scales effectively to PARSEC and SPLASH-2x benchmarks and reduces the errors of architectural events.

In recent years, natural, flexible, and contactless vision-based gesture recognition has received significant attention in human-computer interaction. However, employing convolutional neural networks (CNNs) for RGB or RGB-D gestures can result in excessive power consumption and poor energy efficiency, making them unsuitable for embedded systems. In this paper, we propose a lightweight sparse binarized neural network (sBNN) model for edge gesture recognition that achieves an accuracy of 89.43%-99.92% on four open-source gesture datasets with$\leq 20.26$million operations (MOP) and$\leq 15.83$-Kilobytes (KB) parameters. We find high channel-level sparsity in the activation maps of sBNN when edge gestures are used as inputs. The sparse activation maps have multiple identical activation vectors called sparse activation vectors (SAV), which lead to highly repeated calculations. In order to avoid this issue, we propose a two-stage value prediction approach to skip these calculations, achieving a speedup of 1.03x-1.83x. Moreover, to reduce on- chip memory, the compression technique is applied to the sparse activation maps, providing a compression rate of 1.72x-3.45x. Finally, we implement an energy-efficient sparse BNN accelerator (SBA) on an embedded field-programmable gate array (FPGA). The experimental results show that our SBA has a latency of 26.3-46.8-$\mu \text{s}$, a power consumption of 0.807 W, and an energy efficiency of 536.22-952.70-GOPS/W at 50-MHz frequency. Our SBA offers lower latency, lower power consumption, and higher energy efficiency than previous state-of-the-art gesture recognition accelerators.

The promotion of the HEVC standard has significantly alleviated the burden of network transmission and video storage. However, its inherent complexity and data dependencies pose a significant challenge in achieving high compression efficiency hardware encoder. To tackle this challenge, we propose several hardware-oriented algorithms and achieve a hardware encoder supporting both intra and inter coding. In terms of algorithms, our optimizations focus on intra mode decision, motion estimation (ME), rate estimation, and merge mode estimation. These optimizations reduce the computational complexity and address the data dependencies within and between encoder modules while maintaining an acceptable compression efficiency. As for hardware, we propose an encoder architecture that supports not only 35 intra prediction modes but also ME with an extensive search range of [±64, ±64]. The uniform$4\times 4$engine, 2-D data reuse, and timing schedule for intra and inter coding are presented in this architecture to optimize the hardware resource consumption and throughput. Compared with HM 15.0, the proposed hardware-oriented algorithms lead to a 1.88% and 14.57% increase in BD-Rate under the configurations of all intra and low delay P, respectively. Notably, the BD-Rate outperforms all existing hardware encoders supporting 4K resolution. In a GF 28nm fabrication process, the hardware design achieves a clock frequency of 550MHz, supporting 4K@30fps throughput with a hardware gate count of 3154K and memory usage of 1.02MB, and the proposed architecture demonstrates substantial advantages in terms of area, throughput, and power compared to other studies.

Convolutional Neural Networks (CNNs) have achieved remarkable progress in arbitrary artistic style transfer. However, the model size of existing state-of-the-art (SOTA) style transfer algorithms is immense, leading to enormous computational costs and memory demand. It makes real-time and high resolution hard for GPUs with limited memory and limits the application on mobile devices. This paper proposes a novel arbitrary artistic style transfer algorithm, KBStyle, whose model size is only 200 KB. Firstly, we design a style transfer network where the style encoder, content encoder, and corresponding decoder are custom designed to guarantee low computational cost and high shape retention. Besides, the weighted style loss function is presented to improve the performance of style migration. Then, we propose a novel knowledge distillation method (Symmetric Knowledge Distillation, SKD) for encoder-decoder-based style transfer models, which redefines the knowledge and symmetrically compresses the encoder and decoder. With the SKD, the proposed style transfer network is further compressed by 14 times to achieve the KBStyle. Experimental results demonstrate that the proposed SKD method achieves comparable results with other SOTA knowledge distillation algorithms for style transfer. Besides, the proposed KBStyle achieves high-quality stylized images. And the inference time of the KBStyle on an Nvidia TITAN RTX GPU is only 20 ms when the resolutions of the content image and style image are both 2k-resolution ( 2048×1080 ). Moreover, the 200 KB model size of KBStyle is much smaller than the SOTA models and facilitates style transfer on mobile devices.

Neural radiance field (NeRF) has proved to be promising in augmented/virtual-reality applications. However, the deployment of NeRF on edge devices suffers from inadequate throughput due to redundant ray sampling and congested memory access. To address these challenges, this article proposes Hi-NeRF, a multirendering-core accelerator for efficient edge NeRF rendering. On the architecture level, a hierarchical empty space skipping (HESS) scheme is adopted, which efficiently locates the effective samples with fewer skipping steps and thus accelerates the ray marching process. Furthermore, to alleviate the memory access bottleneck, a vertex-interleaved mapping (VIM) method that eliminates memory bank conflicts is also proposed. On the hardware level, ineffective sample filters (ISFs) and voxel access filters (VCFs) are introduced to further exploit spatial sparsity and data locality at run-time. The experimental results show that our work achieves$2.67\times $rendering throughput and$11.2\times $energy efficiency compared to a SOTA NeRF rendering accelerator. The energy efficiency can be improved by$561\times $compared to a commercial GPU.

The automated diagnosis of breast cancer through Whole Slide Images (WSI) is a critical endeavour to combat the threat it poses to women’s health. However, traditional deep learning algorithms strongly rely on Independent and Identically Distributed (I.I.D) and then encounter challenges related to multi-instance bias when analyzing multiple tissue sections from the same patient, limiting their generalization capability. To address this, this study introduces Multi-Instance Bias Suppression (MIBS), a novel approach leveraging adversarial training to mitigate patient-specific overfitting. MIBS employs an instance-level discriminator to guide feature generation, disentangling instance-specific cues from broader diagnostic patterns. Through competitive adversarial training, MIBS enhances feature generalization, effectively addressing overfitting and boosting cross-patient accuracy. Validated on the BreakHis dataset, MIBS effectively tackles multi-instance bias-induced overfitting. By bridging the gap between cutting-edge deep learning techniques and the challenges posed by large-scale medical image data, MIBS advances the accuracy and applicability of breast cancer diagnosis. Our approach addresses the multi-instance bias challenge and integrates seamlessly with big data, propelling medical image analysis to new heights of efficiency and precision.

In database systems, materialized views (MV) pre-emptively materialize the common portion of query workloads to reduce redundant computations through query rewriting. However, the utilization of these rewritten queries depends on the accuracy of cost estimation models. Despite the promising performance of learning-based cost estimation models, they still exhibit limitations. Firstly, they are unable to capture the relationships between cross-node dependencies and node hierarchy across physical execution plan trees, hindering accuracy improvements. Secondly, they cannot simultaneously support original queries and rewritten queries, thereby limiting compatibility enhancements. In this paper, we introduce TGAE, a cost estimation model employing Graph Attention Network (GAT) to learn cross-node dependencies among physical execution plans. TGAE first utilizes learning embeddings instead of one-hot encoding and then introduces an efficient node feature encoding to facilitate the dynamic creation of base tables tailored to meet the requirements of MV environments. To demonstrate the effectiveness of TGAE, we design and implement AGatMv, a system with view design and exploitation capabilities. Experimental results on two query workloads from the real-world IMDb dataset show significant improvements in cost estimation accuracy and rewrite evaluation correctness compared to PostgreSQL.

The Dynamic Vision Sensor (DVS) is a new type of bionic vision image sensor that offers the advantages of low latency, low power consumption, and high dynamics range compared to conventional sensors. However, background activity (BA) noise will degrade the quality of the DVS output data and lead to unnecessary bandwidth overhead. In dark environments, pixel arrays generate abundant noise, and conventional spatiotemporal filters can hardly achieve satisfactory results. To solve this problem, we exploit the difference in event density distribution between the actual event and noise and propose a denoising method that utilizes the event densities with two neighbors of different radii. Compared to spatiotemporal filters, our approach reduces the error rate on synthetic datasets by at least 35%. Meanwhile, our approach is subjectively more visually appealing. With our denoising method, the performance of DVS can be better in dark conditions.

Traditional video coding technologies compress and reconstruct the video frames, which focus on human perception. However, video coding for machines (VCM) uses the feature stream to bridge the correlation between human perception and machine intelligence for vision tasks. We extract the features for the CU with different shapes with part of resnet architecture for VCM. However, the feature-based methods use the model to complete the forward process, which is very time-consuming for its complex architecture and parameter size. The CU architecture for the feature extraction further increases the operation times. A fast algorithm based on the Histogram of oriented gradient (H OG) is proposed for the video coding for machines with VVC intra to overcome the time-consuming problems while maintaining the performance for the vision tasks with codec. The correlation of the mode decision with the VCM performance is discussed to motivate the fast intra coding for V CM. Moreover, the VTM and VVenc are used to verify the universality of the proposed method. The proposed methods can speed up the fast encoding for 35.21 % time saving with 0.26 increment for AP50 for the cityscapes dataset compared with the VTM10.0.

Dynamic vision sensors (DVS) have significant potential in scenes involving high-speed motion and extreme light. However, DVS is sensitive to background active noise, which will degrade the quality of the output. The ordinary$O(N^{2})$-Space spatiotemporal filter's memory complexity is high. It needs$N\times N$memory cells ($N\times N$is the resolution on the sensor). Some works reduce memory complexity by sacrificing the performance of the filter. To ensure the filtering effect and reduce the filter's memory complexity, this paper proposes a novel filter: Queue-based spatiotemporal filter. Moreover, based on the Queue-based spatiotemporal filter, this paper proposes a clustering algorithm that can cluster while filtering. Experiments show that the proposed filter's performance is similar to the$O(N^{2})$-Space spatiotemporal filter while having a lower memory complexity. Besides, using the proposed clustering algorithm, the objects in motion can be clustered with low calculation complexity.

Non-volatile Compute-in-Memory (CIM), especially high-speed MRAM CIM, promises to be a solution of “Memory Wall” problem in power-sensitive artificial intelligence edge devices. However, the low resistance and low on/off ratio limit the row parallelism and efficiency of MRAM CIM macros. To overcome these challenges, this work proposes the following: 1) a series 3T1MTJ bit-cell CIM architecture; 2) an input-aware and self-generated dynamic reference array; 3) a high-speed readout pipeline circuit. The proposed macro eliminates errors of high Row-Parallel multiply-and-accumulate (MAC) operation with 150 TOPS/W peak energy efficiency simulated using 40nm process and STT-MTJ.

The latest Versatile Video Coding (VVC) standard incorporates a series of effective and complex new intra coding tools, which obtains superior coding efficiency than the High Efficiency Video Coding (HEVC). However, this makes the intra coding more complicated and time-consuming. A fast algorithm for VVC from two aspects of fast mode decision and fast partition decision is proposed in this paper. For the fast mode decision, the relationship between bins with Histogram of Oriented Gradient (HOG) and intra modes is created for the mode selection, decreasing the planar modes for SATD and RDO. Moreover, we analyze the maximum bins to determine the final modes, and we use the modes of left and upper blocks as a reference for the current CU, which can early terminate RDO. Moreover, a two-step fast partition algorithm is proposed based on HOG for fast partition decision, in which two thresholds are investigated to control the uniformity of textures. The proposed fast algorithm is implemented on the VVC test model, and the experimental results show that it can achieve 69.07% time savings with only 2.96% BDBR increases averagely, which outperforms other relatively existing state-of-the-art methods. Moreover, to convince the universality of our algorithm, we further implement our method in Fraunhofer Versatile Video Encoder (VVenc) and Fraunhofer Versatile Video Decoder (VVdec), which have five settings to control the trade-off between encoding quality and efficiency for intra coding. The fast intra mode decision algorithm and fast partition algorithm decrease the complexity of intra coding for both VTM and VVenc, which shows the efficiency and universality of the proposed fast partition and fast mode decision algorithms.

Radiation Hardened by Design (RHBD) is one of the main measures for solving the soft error issue in digital circuits. However, a multi-objective optimization (MOO) problem obviously appears when utilizing the hardened counterparts to replace the original unreliable cells. This paper proposes a MOO framework based on Bayesian Optimization (BO) for balancing design metrics like area, Longest Path Delay (LPD)/power, and Soft Error Rate (SER) while hardening digital circuits, including combinational and sequential circuits. This framework comprises two phases: 1) data preprocessing and 2) multi-objective Bayesian optimization. The first phase makes this framework much more applicable for large-scale circuits through data dimensionality reduction. The second phase is characterized by utilizing a black-box approach to greatly promote the efficiency and accuracy of MOO. Experimental results on benchmark circuits demonstrate that the framework achieves a 1.34x improvement in accuracy, an 11.47x enhancement in efficiency, and a 0.77x reduction in SER, while exhibiting a 4.27x and 0.72x increase in area for combinational and sequential benchmark circuits, respectively, along with a 0.54x increase in LPD and a 1.25x increase in power for Triple Modular Redundancy (TMR) techniques.

With the scaling down of process, single event upset has been a critical issue for integrated circuits. It is much more likely to occur multiple-node upsets (MNUs) in CMOS ICs in advanced technology. However, the problem remains unsolved because of the lack of efficient methods. In this article, a non-redundant triple-node-upset(TNU)-tolerant latch with high reliability is proposed in 28 nm CMOS technology. The proposed latch named KOBE reduces the number of inner-sensitive nodes as well as the redundancy of the TNU-tolerant latch. In simulations, the proposed KOBE latch performs faster and lower power with higher reliability than most of the TNU-tolerant latches proposed before. The post-layout parasitic extracted simulations show that the proposed KOBE latch has an average improvement of 52.5% in a Power-Area-Delay Product (PADP) compared with the recently reported TNU-hardened latch at a supply voltage of 0.9 V, a working temperature of 27 °C. What’s more, by changing the working voltage and temperature, it is proved that the proposed KOBE latch has a better performance in a harsh environment. The results show that the proposed KOBE latch is of high beneficial efficiency and high reliability, thus can be used in safety-critical applications.

A self-biased voltage/current reference (VCR) generator provides bias for its embedded operational amplifier simply by itself. But during the power-up process, it is prone to be trapped into an undesired operating point called Trojan state (TS-UOP) that a conventional startup circuit (CSC) is unable to handle. This paper firstly simulates the power-up process of a self-biased VCR generator and discovers the dominant node that plays the leading role in the power-up convergence. Then, a dominant-node theory is proposed to find the dominant node based on the voltage-vertex directed dependency graph (DDG) and the Weight-Flow algorithm. In order to rescue the dominant node, a Monitoring-Rescue method is proposed as a general approach to enhanced startup circuits (ESCs) to eliminate TS-UOPs. An example of ESCs is designed in a 28-nm CMOS process. The measurement results verify that the ESC successfully helps the self-biased VCR generator converge to the desired operating point (DOP) regardless of the power-up ramping time range of$\mathrm {100~ \mu \text { s} }$to$\mathrm {100~ \text {m} \text { s} }$and the temperature range of$\mathrm {-45~ ^{\circ}C}$to$\mathrm {115~ ^{\circ}C}$.

Computing-in-memory (CIM) relieves the Von Neumann bottleneck by storing the weights of neural networks in memory arrays. However, two challenges still exist, hindering the efficient acceleration of convolutional neural networks (CNN) in artificial intelligence (AI) edge devices. Firstly, the activations for sliding window (SW) operations in CNN still bring high memory access pressure. This can be alleviated by increasing the SW parallelism, but simple array replication suffers from poor array utilization and large peripheral circuits overhead. Secondly, the partial sums from individual CIM arrays, which are usually accumulated to obtain the final sum, introduce large latency due to enormous shift-and-add operations. Moreover, high-resolution ADCs are also needed to reduce the quantization error of partial sums, further increasing the hardware costs. In this paper, a hardware-efficient CIM accelerator, ARBiS, is proposed with improved activation reusability and bit-scalable matrix-vector-multiplication (MVM) for CNN acceleration in AI edge applications. The cyclic-shift weight duplication exploits a third dimension of receptive field (RF) depth for SW weight mapping to reduce the memory accesses of activations, improving the array utilization. The parasitic-capacitance charge sharing is employed to realize high-precision analog MVM in order to reduce the ADC cost. Compared with conventional architectures, ARBiS with parallel processing of 9 SW operations achieves 56.6%~58.8% alleviation of memory access pressure. Meanwhile, ARBiS configured with 8-bit ADCs saves 92.53%~94.53% ADC energy consumption. An ARBiS accelerator is evaluated to realize a computational efficiency (CE) of 10.28 (10.43) TOPS/mm2, an energy efficiency (EE) of 91.19 (112.36) TOPS/W with 8-bit (4-bit) ADCs, achieving$11.4\sim 11.7\times $($11.6\sim 11.8\times $),$1.1\sim 3.3\times $($1.4\sim 4\times $) improvements over state-of-the-art works, respectively.

Denoising is one of the most significant procedures in the image processing pipeline. Nowadays, deep-learning-based algorithms have achieved superior denoising quality than traditional algorithms. However, the noise becomes severe in the dark environment, where even the SOTA algorithms fail to achieve satisfactory performance. Besides, the high computational complexity of deep-learning-based denoising algorithms makes them hardware unfriendly and difficult to process high-resolution images in real-time. To address these issues, a novel low-light RAW denoising algorithm Two-Stage-Denoising (TSDN), is proposed in this paper. In TSDN, denoising consists of two procedures: noise removal and image restoration. Firstly, in the noise-removal stage, most noise is removed from the image, and an intermediate image that is easier for the network to recover the clean image is obtained. Then, in the restoration stage, the clean image is restored from the intermediate image. The TSDN is designed to be light-weight for real-time and hardware friendly. However, the tiny network will be insufficient for satisfactory performance if directly trained from scratch. Therefore, we present an Expand-Shrink-Learning (ESL) method to train the TSDN. In the ESL method, firstly, the tiny network is expanded to a larger one with similar architecture but more channels and layers, which enhances the learning ability of the network because of more parameters. Secondly, the larger network is shrunk and restored to the original small network in fine-grained learning procedures, including Channel-Shrink-Learning (CSL) and Layer-Shrink-Learning (LSL). Experimental results demonstrate that the proposed TSDN achieves better performance (PSNR and SSIM) than other SOTA algorithms in the dark environment. Besides, the model size of TSDN is one-eighth of that of the U-Net for denoising (a classical denoising network).

Although deep learning-based (DL-based) image processing algorithms have achieved superior performance, they are still difficult to apply on mobile devices (e.g., smartphones and cameras) due to the following reasons: 1) the high memory demand and 2) large model size. To adapt DL-based methods to mobile devices, motivated by the characteristics of image signal processors (ISPs), we propose a novel algorithm named LineDL. In LineDL, the default mode of the whole-image processing is reformulated as a line-by-line mode, eliminating the need to store large amounts of intermediate data for the whole image. An information transmission module (ITM) is designed to extract and convey the interline correlation and integrate the interline features. Furthermore, we develop a model compression method to reduce the model size while maintaining competitive performance; that is, knowledge is redefined, and compression is performed in two directions. We evaluate LineDL on general image processing tasks, including denoising and superresolution. The extensive experimental results demonstrate that LineDL achieves image quality comparable to that of state-of-the-art (SOTA) DL-based algorithms with a much smaller memory demand and competitive model size.

In large-scale chip multiprocessors (CMPs), the scalability of a coherence directory becomes more important as the number of cores increases. However, previously proposed scalable coherence directories typically reduce the directory storage overhead at the cost of one or more aspects of performance, accuracy, and complexity. In this article, we propose the tag-sharer-fusion (TSF) directory, a scalable coherence directory with low hardware complexity, as well as with high performance and accuracy. Each directory entry has just enough bits to store a single sharer pointer and is divided into two primary formats:tagandsharer, wheresharerentries store sharers but not tags. Each private block is tracked by atagentry, and each shared block is tracked by a combination of atagentry and asharerentry in the same set. Simulation of a 128-core chip-multiprocessor with the PARSEC and SPLASH-2x benchmarks shows that the TSF directory requires only a quarter of the area of a non-scalable full-map sparse directory to achieve similar performance and network traffic, both with an average overhead within 1%. The TSF directory outperforms the state-of-the-art Pool and way-combining directory proposals in terms of storage overhead, performance, and network traffic.

Video coding plays an important role in the highly information-based world as videos contribute the largest part of network traffic. The latest video coding standard Versatile Video Coding (VVC) introduces a new transform scheme multiple transform selection (MTS), which brings considerable coding gains at the expense of high coding complexity. In this article, we propose a reconfigurable MTS architecture that supports all transform types in VVC with square and rectangular sizes ranging from$4\times $4 to 32$\times32$. Firstly, we explore the features of three types of transform matrices and extract the features that are beneficial to designing a unified architecture. Then, we present an improved calculation scheme for general transforms, where the transform matrix is decomposed into two simpler matrices to increase the similarity and decrease the complexity of matrices involved in three types of transform operations. Thanks to the improved calculated scheme, a unified shift-adder unit (SAU) is designed and highly reused by different types. Moreover, we provide a twirling two-point splicing (T2S) scheme to improve reusability and deal with issues of data mismatch when conducting discrete cosine transform (DCT)-II of different sizes. As a consequence, an architecture with constant throughput of 32 pixels/cycle is implemented and specified in Verilog HDL. The synthesis results indicate that the application specific integrated circuit (ASIC)-based and field-programmable gate array (FPGA)-based hardware architectures achieve significant advantages both in area reduction and power consumption compared to existing methods in the literature.

Recent advances in mobile devices and cloud computing techniques have made it possible to capture, process, and share high resolution, high frame rate (HFR) videos across the Internet nearly instantaneously. Being able to monitor and control the quality of these streamed videos can enable the de-livery of many enjoyable content and perceptually optimized rate control. However, the development of no-reference (NR) VQA algorithms targeting frame rate variations has been little studied. Here, we propose a first-of-a-kind blind VQA model for evaluating HFR videos, which we dub the Framerate-Aware Videos Evaluator w/o Reference (FAVER). FAVER uses extended models of spatial natural scene statistics that encompass space-time wavelet-decomposed video signals, to conduct efficient frame rate sensitive quality prediction. Our extensive experiments on several HFR video quality datasets show that FAVER outperforms other blind VQA algorithms at a reasonable computational cost. The code will be released on https://github.com/uniqzheng/HFR-BVQA.

In this paper, we propose a learned video codec with a residual prediction network (RP-Net) and a feature-aided loop filter (LF-Net). For the RP-Net, we exploit the residual of previous multiple frames to further eliminate the redundancy of the current frame residual. For the LF-Net, the features from residual decoding network and the motion compensation network are used to aid the reconstruction quality. To reduce the complexity, a light ResNet structure is used as the backbone for both RP-Net and LF-Net. Experimental results illustrate that we can save about 10% BD-rate compared with previous learned video compression frameworks. Moreover, we can achieve faster coding speed due to the ResNet backbone.

User-generated contents (UGC) have gained increased attention in the video quality community recently. Perceptual video quality assessment (VQA) of UGC videos is of great significance for content providers to monitor, process, and deliver massive numbers of UGC videos. Blind video quality prediction of UGC videos is challenging since complex mixtures of spatial and temporal distortions contribute to the overall perceptual quality. In this paper, we develop a simple, effective, and efficient blind VQA framework (STS-QA) based on the statistical analysis of space-time slices (STS) of videos. Specifically, we extract spatio-temporal statistical features along different orientations of video STS, that capture directional global motion, then train a shallow quality predictor. The proposed framework can be used to easily extend any existing video/image quality model to account for temporal or motion regularities. Our experimental results on three publicly available UGC databases demonstrate that our proposed STS-QA model can significantly boost prediction performance compared to baselines. The code will be released at: https://github.com/uniqzheng/STS_BVQA.

AVS3 is a newly proposed video coding standard by the Audio Video coding Standard Workgroup, demonstrating higher compression efficiency than the High Efficiency Video Coding standard. Advanced entropy coding is one of the performance bottlenecks of the AVS3 standard video encoder due to the strong data dependency in its arithmetic coding process. A novel arithmetic encoding hardware structure is presented in this paper, and as we know, this is the first paper on AVS3 AEC hardware implementation. Firstly, we select and apply the typical optimization schemes adopted in HEVC context-based adaptive binary arithmetic coding designs. Secondly, Utilizing the unique characteristics of AVS3 AEC, we propose mathematical reordering, variable-clock-cycle range updating and variable-clock-cycle context modeling methods to optimize the critical path. Our design can encode 2.6457 bins per clock cycle, and the corresponding throughput is 3131 Mbin/s in Globalfoundries 28nm process. Compared with the basic anchor structure, it has obtained a performance improvement of 319% and can meet the 8k@l20fps ultra-high-definition video encoding requirements.

The latest Versatile Video Coding (VVC) standard incorporates a series of effective and complex new intra coding tools, which obtains superior coding efficiency than the High Efficiency Video Coding (HEVC). However, this makes the intra coding more complicated and time-consuming. A fast algorithm for VVC is proposed from two aspects of model selection and early terminating to reduce coding complexity in this paper. The relationship between bins with HOG and intra modes is created for the mode selection, decreasing the planar modes for SATD and RDO. Moreover, we analyze the maximum bins to determine the final modes, and we use the modes of left and upper blocks as a reference for the current CU, which can early terminate RDO. The proposed algorithm is implemented on VVC test model, and the experimental results show that it can achieve 36.61% time savings with only 0.94% BDBR increases averagely, which outperforms other relative existing state-of-the-art methods.

Physically Unclonable Functions (PUFs) are emerging security primitives for authentication due to its high physical security. Especially for those with excellent area-efficiency and reliable immunity against attacks, the demand is larger. In order to achieve higher security and area-efficiency, this paper proposes a strong PUF based on resistive random-access memory (RRAM). We exploit both the switching randomness and intrinsic resistance distribution of RRAM to increase the randomness of entropy source, and design a novel strong PUF structure with double-read process to increase the challenge-response pairs (CRPs) and area-efficiency. A double XOR process is proposed to enhance the immunity against machine learning attack (MLA) with low area-overhead. Compared with the state of the art, the number of CRP has been greatly improved, demonstrating a better area-utilization. Simulation results show that the CRP generation time is 1. 8us, mean intra-HD of1.93%, inter-HD of 49.95% and uniformity of 49.02%. The above features of the proposed strong PUF make it a promising candidate for Internet of Things (IoTs) authentication applications.

This paper presents a novel fully synthesizable dynamic latched comparator with reduced kickback noise. A dynamic latched comparator is attractive to low power and high speed applications, but suffers from kickback noise. Although several kickback noise reduction techniques have been widely used, none of them can apply to synthesizable design flow. Inspired by the isolation technique, this paper employs OAI22 (4-input OR-AND-INVERT) gates to replace the NAND3 (3-input NAND) gates in the input stage of the conventional synthesizable dynamic latched comparator, so that the kickback noise can be significantly reduced due to the inherent isolation transistor in OAI22. Simulated in 28nm process, the proposed OAI22-based comparator achieves the maximum kickback noise of 8.63mV, compared with that of 46.16mV in the NAND3-based counterpart.

Carrier phase recovery (CPR) determines the accuracy of the receiver in modern coherent optical communication. The accurate estimation and tracking of carriers are particularly vital with the increase of throughput for long-distance transmit. It is a challenge to implement a real-time system because the computational complexity increases with fractional bits. Moreover, the conversion between polar coordinates and Cartesian coordinates introduces a high latency. In this paper, we present an FPGA implementation of low latency Viterbi-Viterbi 4thPower Estimation (VV4E) based CPR, which mainly performs the computation in Cartesian coordinates and implements the trigonometric function with a look-up table (LUT). Evaluations on Xilinx ZCU102 show that at a frequency of 370MHz, it introduces a 22-cycle latency to handle the 29.6 GBd QPSK signals, which is the minimum value to our knowledge.

Convolutional neural network (CNN)-based in-loop filtering have been very successful in video coding. For most existing works, however, a specific model was required for each quantization parameter (QP) band. In this paper, we introduce a generic method for helping CNN-filters deal with variable quantization noises. A feasible solution to this problem can be implemented on CNN by introducing a quantization step (Qstep) into the CNN. As the quantization noise changes, the CNN filter’s ability to suppress noise changes accordingly. The (vanilla) convolution layer can be replaced directly by this method in existing CNN filters. Compared with the VVenC anchor, only one CNN filter is used and achieves about 3.6% BD-rate reduction for the luminance component of random-access configuration. Also, about 0.8% BD-rate reduction has been achieved compared with the previous QP-map method.

EMG based hand gesture recognition on convolutional neural networks (CNNs) has been widely learned, which gains high accuracy. However, CNN based systems are computationally complex and power consuming, thus hard to be deployed at edge. Biologically inspired, a new neuromorphic learning and computing approach for electromyogram (EMG) based hand gesture recognition tasks is proposed in this work. This approach designs an activate and inhibit joint processing spiking neural network (AIPS-SNN) which reaches an accuracy of 85.6% on Nina Pro dataset. Furthermore, the AIPS-SNN is deployed on the proposed memristor based computation in-memory (CIM) system, the power efficiency and area efficiency of which reach 10.146 TOPS/W and 35.399 GOPS/mm2, respectively. The experimental results indicate that the proposed neuromorphic CIM engine is promising for edge deployment.

This paper presents a triple-output piezoelectric energy harvesting (PEH) system with parallel synchronized switch harvesting on capacitors (P-SSHC) rectifier based on shared capacitors. By analyzing the principle of the P-SSHC rectifier, this paper supports the rationality of using shared capacitors to construct the multi-voltage conversion ratio (VCR) switch capacitor (SC) DC-DC converters. In addition, the adoption of a parallel structure in the multi-output SC DC-DC converters reduces the cross-regulation. Simulation results show that the proposed system not only has good input power adaptability (1/3X,1X,2X) but can also provide triple voltage (0.5V, 1V, 2V) with less cross-regulation. The maximum output power is 14.4μW when peak-to-peak open circuit voltage is 1.7V.

This paper presents the first synthesis friendly dynamic amplifier (DA). The proposed fuzzy logic calibration makes its gain robust against process-voltage-temperature (PVT). In addition, the piecewise-linear linearization technique is also proposed for the fuzzy logic to tune the amplification phase, which compensates the time-domain non-linearity of the regeneration voltages, and accelerates the calibration convergence. The proposed DA is designed in 28-nm CMOS process, and verified by post-simulation results. It has a 16 × gain with -3.0%~3.6% deviations at TT corner once the calibration converges within 50 cycles.

This paper proposes a piezoelectric energy harvesting interface circuit using multiple charge extractions and the multiple precharge (MCE-MPC) technique. This circuit is able to extract energy from PEH efficiently using a miniscule inductor and has the advantage of controllable precharge energy. It improves output power and extraction efficiency by using precharge and multiple transfers techniques. When the inductor value is 50μH, the output power of MCE-MPC is increased by 101.92% and 24.60% compared with synchronous electric charge extraction (SECE) and multi-shot SECE (MCE), respectively, and 7.62% compared with multiple charge extractions with bias-flip (MCEBF) when precharging the piezoelectric voltage to the same value. When the inductor value is 1mH, an extraction efficiency of 102.9% can be obtained by MCE-MPC.

A self-biased voltage/current reference (VCR) generator is simple, but suffers from some Trojan states surviving the conventional start-up process. After demonstrating this problem by simulation, this paper reveals the mechanism by identifying and analyzing all of the feedback loops that give rise to multiple Trojan states. Based on the theory, an enhanced start-up circuit is proposed that is capable of removing all Trojan states. Finally, the enhanced start-up circuit is embedded into a self-biased voltage reference generator, and designed in 28 nm CMOS process. The simulation results prove that the enhanced start-up circuit successfully eliminates all Trojan states in a wide temperature range for different process corners.

To speedup the image classification process which conventionally takes the reconstructed images as input, compressed domain methods choose to use the compressed images without decompression as input. Correspondingly, there will be a certain decline about the accuracy. Our goal in this paper is to raise the accuracy of compressed domain classification method using compressed images output by the NN-based image compression networks. Firstly, we design a hybrid objective loss function which contains the reconstruction loss of deep feature map. Secondly, one image reconstruction layer is inte-grated into the image classification network for up-sampling the compressed representation. These methods greatly help increase the compressed domain image classification accuracy and need no extra computational complexity. Experimental results on the benchmark ImageNet prove that our design outperforms the latest work ResNet-41 with a large accuracy gain, about 4.49% on the top-1 classification accuracy. Besides, the accuracy lagging behinds the method using reconstructed images is also reduced to 0.47 %. Moreover, our designed classification network has the lowest computational complexity and model complexity.

Automatic video quality assessment of user-generated content (UGC) has gained increased interest recently, due to the ubiquity of shared video clips uploaded and circulated on social media platforms across the globe. Most existing video quality models developed for this vast content are trained on large numbers of samples labeled during large-scale subjective studies, which are often fail to exhibit adequate generalization abilities on unseen data. Moreover, large labeled video quality datasets are not always available for every scenario, and may not address the coincident evaluation of social videos and the distortions that afflict them. Because of this, it is also desirable to develop opinion-unaware, “completely blind” video quality models, that are free of training, yet can compete with existing learning-based models. Here we propose such a model called VIQE (VIdeo Quality Evaluator), which we designed based on a comprehensive analysis of patch- and frame-wise video statistics, as well as of space-time statistical regularities of videos. The statistical features desired from the analysis capture complementary predictive aspects of perceptual quality, which are aggregated to obtain final video quality scores. Extensive experiments on recent large-scale video quality databases demonstrate that VIQE is even competitive with state-of-the-art opinion-aware models. The source code is being made available athttps://github.com/uniqzheng/Complete-Blind-VQA.

The latest High Efficiency Video Coding standard achieves twice the coding efficiency of the H264 standard through a complex rate-distortion optimization (RDO). The coded bit-streams are produced with context adaptive binary arithmetic coding (CABAC). CABAC itself is a very time-consuming process that includes binarization, context modeling, interval subdivision, renormalization, outstanding bit handling, and context updating. The aim of this research is to speed up the CABAC process through several simplifications. First, we approximate three parts of the CABAC, i.e., interval subdivision, renormalization, and outstanding bit handling, with a piecewise-linear function that is very friendly to hardware implementation. In order to achieve better hardware parallelism, we also improve the coding process at the sub-block level. The context of syntax elements in a sub-block is redistributed to skip the complex calculation of context indexing. We perform context updating at the granularity of sub-blocks so that the data dependency of the context updating is removed completely, and the original serial encoding process is changed to a parallel encoding process. At the same time, we make another simplification for the context modeling ofcu_skip_flag. Based on these simplifications, we build a parallel hardware architecture for the rate estimation of the RDO process. This architecture completes the bit estimation of a$32\times 32$coding tree unit (CTU) in 220.8 nano-seconds, whereas the Bjøntegaard Delta rate increases by only 2.225%. We believe that the proposed architecture can meet the requirements of 8K@120 fps ultra-high-definition videos. This is the first study to simplify the hardware design of rate estimation by changing the context allocation and updating rules.

Although it has been surpassed by many subsequent coding standards, JPEG occupies a large storage share of the current data hosting service. To reduce the storage costs, DropBox proposed a secondary lossless compression algorithm, Lepton, to further improve the compression rate of JPEG images. However, the bloated probability models defined by Lepton severely restrict its throughput and energy efficiency. To solve this problem, we construct an access probability-based hash function for the probability models, and then propose a hardware-friendly memory optimization method by combining the proposed hash function with N-way Set-Associative unit. Besides, we also propose a synchronization mechanism for the serial accessing probability model, so that the syntax elements can be processed in parallel without changing the resulting bitstream. After that, we implement a high throughput, high energy efficiency, and low-cost Lepton hardware encoder. To the best of our knowledge, this is the first hardware implementation of transparent image recompression. The synthesis result shows that the proposed hardware structure reduces the total area of the probability models by 70.97%. Compared with DropBox’s software solution, the throughput and the energy efficiency of the proposed Lepton hardware encoder are increased by 63 and 1398 times on average. In terms of manufacturing cost, the proposed Lepton hardware encoder is also lower than the general-purpose CPU used by DropBox.

Convolutional neural network (CNN)-based filters have achieved great success in video coding. However, in most previous works, individual models were needed for each quantization parameter (QP) band, which is impractical due to limited storage resources. To explore this, our work consists of two parts. First, we propose a frequency and spatial QP-adaptive mechanism (FSQAM), which can be directly applied to the (vanilla) convolution to help any CNN filter handle different quantization noise. From the frequency domain, a FQAM that introduces the quantization step (Qstep) into the convolution is proposed. When the quantization noise increases, the ability of the CNN filter to suppress noise improves. Moreover, SQAM is further designed to compensate for the FQAM from the spatial domain. Second, based on FSQAM, a QP-adaptive CNN filter called QA-Filter that can be used under a wide range of QP is proposed. By factorizing the mixed features to high-frequency and low-frequency parts with the pair of pooling and upsampling operations, the QA-Filter and FQAM can promote each other to obtain better performance. Compared to the H.266/VVC baseline, average 5.25% and 3.84% BD-rate reductions for luma are achieved by QA-Filter with default all-intra (AI) and random-access (RA) configurations, respectively. Additionally, an up to 9.16% BD-rate reduction is achieved on the luma of sequence BasketballDrill. Besides, FSQAM achieves measurably better BD-rate performance compared with the previous QP map method.

Recently, Deep Convolutional Neural Networks (DCNNs) have achieved remarkable progress in computer vision community, including in style transfer tasks. Normally, most methods feed the full image to the DCNN. Although high-quality results can be achieved in this manner, several underlying problems arise. For one, with the increase in image resolution, the memory footprint will increase dramatically, leading to high latency and massive power consumption. Furthermore, these methods are usually unable to integrate with the commercial image signal processor (ISP), which processes the image in a line-sequential manner. To solve the above problems, we propose a novel ISP-friendly deep learning-based style transfer algorithm: SequentialStyle. A brand new line-sequential processing mode is proposed, where the image is torn into strips, and each strip is sequentially processed, contributing to less memory demand. We further propose a Spatial-Temporal Synergistic (STS) mechanism that decouples the previously simplex 2-D image style transfer into spatial feature processing (in-strip) and temporal correlation transmission (in-between strips). Compared with the SOTA style transfer algorithms, experimental results show that our SequentialStyle is competitive. Besides, SequentialStyle has less demand for memory consumption, even for the images whose resolutions are 4 k or higher.

Single Event Upset (SEU) is one of the most susceptible reliability issues for CMOS circuits in a harsh environment, such as space or even a sea-level environment. Especially in the advanced nanoscale node, the phenomenon of Multi-node-upset (MNU) becomes more prominent. Although a lot of work has been proposed to solve this problem, most of them ignored the need for low power consumption. Particularly, most existing solutions are not effective anymore when operating in low supply voltage. Therefore, this paper proposes a novel Flip-Flop called TRIGON based on a single-phase-clocking structure to achieve low power consumption while being able to tolerate Double-node-upset (DNU), even when operating at lower supply voltages. The experimental results show that TRIGON has a significant reduction in the area and Power-delay-area-product (PDAP). Particularly, it achieves about 80% energy saving on average when the input is static compared with the state-of-the-art circuits.

Since deep learning was introduced into style transfer, remarkable results have been achieved in it and it is widely used in multimedia fields, such as photography. However, the computational costs of the existing state-of-the-art (SOTA) arbitrary style transfer algorithms are still too complex to apply them on mobile device and high resolution, and their performance on shape retention is not satisfactory enough. To deal with the above problems, we propose a novel arbitrary style transfer algorithm. Specially, we propose a new network which ensures the low computational cost and high shape retention. Moreover, we propose the weighted style loss function to improve the performance on style migration. The experimental results show that the proposed algorithm achieves better results with lower computational cost than the SOTA algorithms.

Conventional hardened cells are not robust enough to single event upset (SEU) in 28nm technology due to the scaling of the transistors. High soft error rate is caused by particle striking at cells and logic circuit in SRAM. This work proposes an SEU robust dual access 12T (DA-12T) SRAM with a radiation hardened crossbar-based peripheral circuit (CBPC). The proposed cell with 209% area penalty is more SEU robust than most cells. The CBPC can reduce the read failure rate of SRAMs. The new sense amplifier ensures the correct and rapid reading operation speed when suffering read disturbance. The experiment results show that the SEU cross-section of proposed cell is 60% of standard cell with dummy. Almost no read failure is observed in SRAM with CPBC when operational frequency exceeds 40MHz. Further investigation indicated that DA-12T cell and well isolation technique can reduce the read failure rate.

With the continuous scaling-down of transistors, the soft error issue of the combinational circuit becomes more serious. Triple Modular Redundancy (TMR) and Gate-Sizing (GS) are commonly used hardening methods for combinational circuits. However, the traditional TMR method is often applied at the module level, causing a large area overhead. Therefore, to explore the feasibility of refined and more general TMR, a General Efficient TMR (GE-TMR) method is proposed in this paper. Furthermore, since the hardening process is a multi-objective optimization problem, a Solution Distribution Optimized NSGA-II (SDON) algorithm is proposed. It features a trade-off between Soft Error Rate (SER), delay, and area. Based on the SDON, we systematically characterized and compared the three hardening methods, which are GE-TMR, GS, and MIX (a hybrid application of GE-TMR and GS). The experimental results show that GE-TMR can provide lower SER solutions (SER reduction >88%) than GS (SER reduction >85%) when the area overhead >200%. By combining GE-TMR and GS, in the interval of 100%81%) than the two hardening methods optimized separately (SER reduction of 64% and 80% for GE-TMR and GS, respectively).

Soft error is a major reliability concern in advanced technology nodes. Although mitigating Soft Error Rate (SER) will inevitably sacrifice area and power, few studies paid attention to optimization methods to explore trade-offs between area, power and SER. This paper proposes an optimization framework based on Bayesian approach for soft-error-tolerant circuit design. It comprises two steps:1) data preprocessing and 2) Bayesian optimization. In the preprocessing step, a strategy incorporating k-means algorithm and a novel sequencing algorithm is used to cluster Flip-Flops (FFs) with similar SER in order to reduce the dimensionality for the subsequent step. Bayesian Neural Network (BNN) is the applied surrogate model for acquiring the posterior distribution of three design metrics, while the Lower confidence bound (LCB) functions are employed as acquisition functions to select the next point based on BNN when optimizing. Finally, the non-dominated sorting genetic algorithm (NSGA-II) is used to search the Pareto Optimal Front (POF) solutions of three LCB functions. Experimental results demonstrate the proposed framework has a 1.4x improvement in accuracy and a 70% reduction in SER with acceptable increases in power and area.

This paper presents a methodology of the clock polarity inversion (CPI) technique to design integer and halfinteger frequency dividers. Based on a generalized structure of CPI dividers, the CPI-state allocation algorithms are derived for a CPI divider to achieve desired division ratio and duty cycle. The methodology is then demonstrated by a programmable CPI divider that is designed in a 65-nm CMOS process and verified by measurements.

Images taken outdoor often experience degradation due to the influence of haze. A lot of algorithms have been proposed to solve this problem. One kind of algorithms are based on some hand-crafted features, which often work only in the situations where those hand-crafted features are valid. There are also some algorithms, which use deep learning-based methods to recover clear images, but they depend on the 2D images, and their run time increases rapidly when the size of images gets larger. Moreover, these models need a large dataset to be trained. In this study, we proposed a novel way based on deep learning and histogram matching to overcome these common problems. Firstly, we develop a network with 1D ResNet structure to predict the histogram of a recovered image. Secondly, we match the histograms of the inputs to the outputs of the model, which are processed patch by patch, to get a series of clear patches. Finally, we use an image-guided filter to overcome the unnatural transition between patches. Experiments on both synthetic and real-world hazy images show that our method performs about 3% better in terms of SSIM(structural similarity index) and 15% better in terms of CIEDE2000 than some state-of-the-art methods on a synthetic hazy image dataset. Furthermore, our model runs faster than other deep-learning-based algorithms in our experiments by about 187% to 382%.

Finding enough accurate matching points is key for image stitching. However, the existing state-of-the-art algorithms fail to find enough accurate matching points when facing the challenge where detectable features are not obvious. In this paper, a novel algorithm called CNN-MP is proposed to directly obtain Matching Points between two images using the feature maps extracted by Convolution Neural Network (CNN) and CNN-MP skips the step of detecting keypoints. There are mainly five contributions in CNN-MP: 1) break the conventional image stitching steps without detecting keypoints; 2) a feature map calculation model is built to obtain matching points between the feature maps of two images; 3) establish a position model to map the obtained matching points to the original images; 4) the process of obtaining matching points is accelerated by dividing it into pre-locate and fine-locate; 5) establish the dataset to evaluate CNN-MP in the case where detectable features are not obvious. The experimental results show that the number of accurate matching points obtained by the proposed CNN-MP is at least 1.7 times that of the state-of-the-art algorithms: ORB, SIFT, LIFT and SuperPoint when facing the challenge where detectable features are not obvious. Moreover, CNN-MP also achieves good performance when the input images own significant detectable features.

This work presents the novel integration of a reconfigurable piezoelectric energy harvester array (RPA) with a parallel synchronized switch harvesting on inductor (P-SSHI) rectifier. The proposed design realizes maximum power point tracking (MPPT) by adjusting RPA with changes in vibration amplitude. Compared with the traditional interface systems based on monolithic piezoelectric energy harvester (PEH), this design can operate in a wider range of input voltage, removing the need for a DC-DC converter, essential in the traditional design. This adaptability eliminates the need for extra-passive components and reduces switching loss. RPA can be also configured in series to reduce the inherent capacitance of PEHs, effectively improving the extraction efficiency of P-SSHI rectifier. Simulations of this system show that the efficiency of the RPA/P-SSHI combined system can be kept above 66% within an input voltage range from 0.03V to 4.39V.

This paper presents a synthesis friendly digital-like delta sigma (ΔΣ) analog-to-digital converter (ADC) based on voltage-controlled oscillator (VCO). The VCO is improved for low power and easiness of calibration. The proposed calibration technique establishes an extra feedback loop to prevent the center frequency of VCO from process variation. Taking the digital-like analog/mixed-signal (AMS) design flow, a 750MS/s ΔΣ ADC is designed in both 28nm and 65nm CMOS technologies with process variation tolerance and process migration verified by post-layout simulation. It is fabricated in 65nm CMOS technology and verified by measurement.

For the next-generation video coding standard Versatile Video Coding (VVC), several new contributions have been proposed to improve the coding efficiency, especially in the transformation operations. This paper proposes a unified $32\times 32$ block-based transform architecture for the VVC standard that enables 2D Discrete Sine Transform-VII (DST-VII) and Discrete Cosine Transform-VIII (DCT-VIII) of all sizes. It mainly gives three contributions: 1) The N-Dimensional Reduced Adder Graph (RAG-n) algorithm is adopted to design the minimal adder-oriented computational units. 2) The storage of the asymmetric transform units can be realized in the dual-port SRAM-based transpose memory. 3) The pipelined 2D transformations of mixed block sizes are achieved with the throughput rate of 32 samples per cycle. The synthesis results indicate that this architecture can reduce area by up to 73.1% compared with other state-of-the-art works. Moreover, power saving ranging from 4.9% to 9.9% can be achieved. Regarding the transpose memory, at least 21.9% of the area can be saved by using SRAM.

The JPEG is one of the most widely used lossy image-compression standards, whose compression performance depends largely on a quantization table. In this work, we utilize a Convolutional Neural Network (CNN) to generate an image-adaptive quantization table in a standard-compliant way. We first build an image set containing more than 10,000 images and generate their optimal quantization tables through a classical genetic algorithm, and then propose a method that can efficiently extract and fuse the frequency and spatial domain information of each image to train a regression network to directly generate adaptive quantization tables. In addition, we extract several representative quantization tables from the dataset and train a classification network to indicate the optimal one for each image, which further improves compression performance and computational efficiency. Tests on diverse images show that the proposed method clearly outperforms the state-of-the-art method. Compared with the standard table at the compression rate of 1.0 bpp, the regression and classification network provide average Peak Signal-to-Noise Ratio (PSNR) gains of nearly 1.2 and 1.4 dB. For the experiment under Structural Similarity Index Measurement (SSIM), the improvements are 0.4% and 0.54%, respectively. The proposed method also has competitive computational efficiency, as the regression and classification network only take 15 and 6.25 milliseconds, respectively, to process a 768 W 512 image on a single CPU core at 3.20 GHz.

Conventional radiation-hardened cells of static random access memory (SRAM) are not robust enough in 28 nm technology, due to partial immunity of single-event upset (SEU) effect (Quatro-based cells) or insufficient critical charges in sensitive nodes (conventional stacked cells). The reduction of read noise margin (RNM) at the low supply voltage (VDD) confines these cells from low VDD applications. We propose a novel interleaving stacked-14T (ILS-14T) cell which prevents voltage transient from propagating to other redundancies. The ILS-14T cell can be resilient to both 0-1 and 1-0 upsets by injecting 12 mA in sensitive nodes. The critical charges of the ILS-14T cell are substantially larger than most other hardened cells at VDD from 0.3 to 0.9 V. The RNM of the ILS-14T cell is two times of most Quatro-based cells at 0.3 V VDD and larger than most cells at 0.6 and 0.9 V VDD. The area of occupation is 334% of the conventional 6T cell, which equals other 14T cells. The static-dynamic decoder array with 20%-40% area penalty and 116%-132% delay of rising edge, when compared with the conventional one, reduces the read failure rate by preventing single event transients (SETs) from propagating to unexpected word lines (WLs).

Aimed at improving the resistance against power analysis attacks, a systematic and architectural design approach for multicore processors is proposed in this article and is demonstrated in an eight-core prototype platform with low performance overhead and hardware cost. In order to introduce randomness in both the time dimension and the amplitude dimension and make realignment extremely difficult, the proposed multicore platform leverages several methods together, such as random task scheduling (RTS), random insertion of operations (RIO), and frequency and phase randomization (FPR). Moreover, a power state monitoring and control (PSMC) scheme is proposed to defend against power analysis attacks by keeping enough background noises. A test chip of the proposed multicore processor is fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm CMOS LP technology and can operate at up to 800 MHz with a 1.2-V supply. The Advanced Encryption Standard (AES) algorithm with these randomization methods is implemented on the processor. Measurement results show that the correlation power analysis (CPA) attacks and the power analysis attacks based on convolutional neural networks (CNNs) are unsuccessful even with 2 000 000 power traces when all the countermeasures are used.

Matting is a fundamental computer vision problem, which has wide applications from daily life to professional fields. To get more precise matting result, we propose a deep learning based algorithm. The network called very deep residual network (VDRN). The first stage is designed to capture entire foreground object by an improved encoder-decoder architecture. It consists of a deep residual encoder and a sophisticated decoder. The second stage is a fully residual convolutional network used for recovering fine structure like hair. Experimental results show our algorithm can tackle complicated foreground textures even it has similar color with background. We evaluate our algorithm on alphamatting.com online benchmark, and Composition-1k dataset. The results demonstrate our method outperforms previous methods, especially in tackling fine structure.

This paper presents a novel HEVC intra prediction VLSI architecture for 8K video decoding, which supports all 35 intra prediction modes. First, a 32 pixels/cycle intra predictor is proposed, which is designed to adapt to the output format of inverse discrete cosine transform (IDCT), and the prediction shape can be one row of 1 × 32 pixels, two rows of 1 × 16 pixels, four rows of 1 × 8 pixels, or four rows of 1 × 4 pixels, depending on the transform unit (TU) size. The throughput is twice as the latest works and the IDCT-adapted architecture can improve the parallelism and reduce the logic area & memory of the HEVC decoder system. Besides, a 0.8 Kb horizontal and vertical line buffer is proposed to buffer all the required reference samples, only 15% of previous works. And the prediction of Planar and angular mode are merged to share the multiplier and save logic area. Finally, the proposed architecture is synthesized with the TSMC 65nm process with 66.2k logic gates under 400MHz working frequency.

In this paper, a dual learning-based method in intra coding is introduced for PCS Grand Challenge. This method is mainly composed of two parts: intra prediction and reconstruction filtering. They use different network structures, the neural network-based intra prediction uses the full-connected network to predict the block while the neural network-based reconstruction filtering utilizes the convolutional networks. Different with the previous filtering works, we use a network with more powerful feature extraction capabilities in our reconstruction filtering network. And the filtering unit is the block-level so as to achieve a more accurate filtering compensation. To our best knowledge, among all the learning-based methods, this is the first attempt to combine two different networks in one application, and we achieve the state-of-the-art performance for AI configuration on the HEVC Test sequences. The experimental result shows that our method leads to significant BD-rate saving for provided 8 sequences compared to HM-16.20 baseline (average 10.24% and 3.57% bitrate reductions for all-intra and random-access coding, respectively). For HEVC test sequences, our model also achieved a 9.70% BD-rate saving compared to HM-16.20 baseline for all-intra configuration.

Quadtree with nested multi-type tree (QTMT) partition structure in Versatile Video Coding (VVC) contributes to superior encoding performance compared to the basic quad-tree (QT) structure in High Efficiency Video Coding (HEVC). However, the improvement of performance leads to an un-avoidable increase of computational complexity. To achieve a balance between coding efficiency and compression quality, we propose a fast intra partition algorithm based on variance and gradient to solve the rectangular partition problem in VVC. First, further splitting of smooth areas is terminated. Then, QT partition is chosen depending on the gradient features extracted by Sobel operator. Finally, one partition from five possible QTMT partitions is directly chosen by computing the variance of variance of sub-CUs. The theoretical basis of our method is that a homogeneous area tends to be predicted with a larger coding unit (CU), and sub-parts of a split CU are prone to have different textures from each other. To our knowledge, this is the first attempt to apply traditional method to accelerating the rectangular partition problem in VVC intra prediction. Experimental results show that the proposed method can save averagely 53.17% encoding time with only 1.62% BDBR increase and 0.09dB BDPSNR loss compared to anchor VTM4.0.

In the versatile video coding (VVC) proposed by the Joint Video Exploration Team (JVET), the quad-tree with the nested multi-type tree (QTMT) partition scheme has been adopted based on the quadtree structure in the high efficiency video coding (HEVC). The video coding quality of VVC is better than the HEVC, but the algorithm complexity has also increased greatly. In this work, we present an adaptive CU split decision for intra frame with the pooling-variable convolutional neural network (CNN), targeting at various coding unit (CU) shape. The shape-adaptive CNN is realized by the variable pooling layer size where we can make the most of the pooling layer in CNN and retain the original information. Based on the proposed CNN, the CU split or not will be decided by only one trained network, same architecture and parameters for the CUs with multiple sizes. Moreover, with the proposed shape-based CNN training scheme, the various training sample size can be processed successfully. The CUbased network can avoid the full rate-distortion optimization for the CU split and the CU-level rate control can also be enabled. The experiment results show that the proposed method can save 33% coding time with only 0.99% Bjontegaard Delta bitrate (BD-rate) increase.

The advent of Ultra High Definition (UHD) and Super Hi-Vision (SHV) videos has motivated the development of advanced video coding standard in these years. Integer motion estimation (IME) is the most computationally expensive process of High Efficiency Video Coding (HEVC), which is one of the most widespread video coding standards. Many previous works related to IME put emphasis on enlarging search range and improving computation complexity. However, the fact that the IME algorithm should be adaptive to different scenarios was neglected. In view of this, a configurable IME engine and its micro-code-based hardware design are proposed in this paper. Three different search schemes based on our IME engine are evaluated using the HEVC test model (HM) 16.9, achieving an average BD-rate increase of 0.55/-0.07/-0.14%. The hardware design is implemented with 225. 7K gates at 500MHz using TSMC 65nm CMOS standard-cell libraries.

Neural associative memory (AM) is one of the critical building blocks for cognitive computing systems. It memorizes (learns) and retrieves input data by information content itself. One of the key challenges of designing AM for intelligent devices is to expand memory capacity while using a minimal amount of hardware and energy resources. However, prior arts show that memory capacity increases slowly, i.e., in square root with the total number of synaptic weights. To tackle this problem, we propose a synapse model called recursive synaptic bit reuse, which enables near-linear scaling of memory capacity with total synaptic bits. Our model can also handle input data that are correlated more robustly than the conventional model. We evaluated our model in the context of Hopfield neural networks (HNNs) that contain 5-327-KB data storage for synaptic weights. Our model can increase the memory capacity of HNNs as large as 30× over the conventional ones. The very large scale integration implementation of HNNs in 65 nm confirms that our proposed model can save up to 19× area and up to 232× energy dissipation as compared to the conventional model. These savings are expected to grow with the network size.

A nondestructive column-selection-enabled 10T SRAM for aggressive power reduction is presented in this brief. It frees a half-selected behavior by exploiting the bitline-shared data-aware write scheme. The differential-VDD (Diff-VDD) technique is adopted to improve the write ability of the design. In addition, its decoupled read bitlines are given permission to be charged and discharged depending on the stored data bits. In combination with the proposed dropped-VDD biasing, it achieves the significant power reduction. The experimental results show that the proposed design provides the 3.3× improvement in the write margin compared with the standard Diff-10T SRAM. A 5.5-kb 10T SRAM in a 65-nm CMOS process has a total power of 51.25 μW and a leakage power of 41.8 μW when operating at 6.25 MHz at 0.5 V, achieving 56.3% reduction in dynamic power and 32.1% reduction in leakage power compared with the previous single-ended 10T SRAM.

A novel 2-D digital predistortion (DPD) algorithm for fully digital Cartesian transmitter is proposed. The nonlinearity of the digital power amplifier in the digital transmitter necessitates DPD for linearization. In order to shorten the setup time of predistortion coefficients in the lookup table (LUT), a profile inversion-based method is adopted. Compared to the traditional adaptive iterative method, the profile inversion method for DPD in this paper shortens the setup time to 15 μs, which is possible for Long Term Evolution (LTE) time division duplex digital transmitter system to execute calibration within every frame. The algorithm is experimentally verified in a fully digital transmitter implemented in 65-nm general process CMOS technology with LUT size of 0.19 mm2, chip size of 2.7 mm2. The digital transmitter has achieved -35- and -32-dBc adjacent channel leakage ratio with 10-MHz LTE and 20-MHz 802.11g WiFi baseband feed in signals, respectively. The DPD improves the linearity of the transmitter by 21 dB for a 2-D constellation signal.

Neural network has been one of the most useful techniques in the area of image analysis and speech recognition in recent years. Long Short-Term Memory (LSTM), a popular type of recurrent neural networks (RNNs), has widely been implemented on CPUs and GPUs. However, software implementation cannot offer large parallelism for the complicated computation of LSTM, and most of the LSTM hardware implementations proposed yet are intensive and non-configurable. In order to accelerate the computation and reduce the resources consumption, in this work, we present a compact and configurable LSTM neural network hardware architecture. To meet the requirements of different networks, we set a wide array of hardware parameters that can be configured to balance area, power and performance. And we adopt the second-order polynomial to approximate the activation functions in LSTM, which balances the computational accuracy and resource utilization, Implemented on XCZU6EG FPGA running at 238 MHz, our work has a performance of 7.64 GOP/s. Compared to the implementation on Intel Xeon E5-2620 CPU at 2.10 GHz, our parallel hardware architecture achieves 90× speedup for a small network and 25 x speed-up for a large one. The total consumption of resources is 77% less than the state-of-the-art works', which implies the compactness of our work.

In this paper, an automated task partition method for multi-core system is proposed. To explore the full parallelism of an application written in sequential languages such as C/C++, we first present a coarse-grain intermediate representation called Function-ANd-Statement (FANS) which takes function call structure as well as statement structure into account. Based on the FANS intermediate representation, we propose a node fusion technique called Stratify And Grain-Controlled Fusion (SAGCF) to partition the whole application into many subtasks with the goal of maximizing parallelism in space and time dimensions as well as minimizing communication. All of these proposed techniques are implemented in an open source Automatic Task Partition Framework (ATPF). Finally, the feasibility of the proposed method is demonstrated by several cases.

High Efficiency Video Coding (HEVC), the latest video coding standard, aims to provide coding performance that is much superior to that of its predecessor, H.264, especially for high definition video. To fulfill this goal, the inter-prediction unit (PU) partitions of HEVC are more complex, and the search range of motion estimation (ME) is much larger. As a result, ME becomes a bottleneck in the design of the HEVC inter predictor. In response to this challenge, we developed a hardware-oriented integer ME algorithm and the related hardware implementation. Our proposed algorithm led to a decrease in terms of the Bjontegaard Delta rate when compared with the HEVC test model 15.0. The corresponding hardware solution benefitted from 2-D data reuse supported by horizontal and vertical reference SRAMs, on-chip memory reduction supported by 4 × 4 block compression, and a low-power sum of absolute difference (SAD) tree supported by PU-level chip selection. When adopting a 32 × 32 SAD tree, the minimum and maximum required working frequency for 4K × 2K at 30 frames/s videos was [375, 500] MHz. These results demonstrated that our proposed solution offered desirable improvement in both coding speed and coding performance.

Neural associative memory (AM) is one of the critical building blocks for cognitive workloads such as classification and recognition. It learns and retrieves memories as humans brain does, i.e., changing the strengths of plastic synapses (weights) based on inputs and retrieving information by information itself. One of the key challenges in designing AM is to extend memory capacity (i.e., memories that a neural AM can learn) while minimizing power and hardware overhead. However, prior arts show that memory capacity scales slowly, often logarithmically or in squire root with the total bits of synaptic weights. This makes it prohibitive in hardware and power to achieve large memory capacity for practical applications. In this paper, we propose a synaptic model called recursive synaptic bit reuse, which enables near-linear scaling of memory capacity with total synaptic bits. Also, our model can handle input data that are correlated, more robustly than the conventional model. We experiment our proposed model in Hopfield Neural Networks (HNN) which contains the total synaptic bits of 5kB to 327kB and find that our model can increase the memory capacity as large as 30X over conventional models. We also study hardware cost via VLSI implementation of HNNs in a 65nm CMOS, confirming that our proposed model can achieve up to 10X area savings at the same capacity over conventional synaptic model.

By using stochastic computation, a fully-parallel low-density parity-check (LDPC) decoder can be implemented using a lower wire complexity. In order to enhance the decoder performance, probability tracers, such as up/down counters, are added at each edge between variable nodes and check nodes, as described in previous literature. However, this causes a large decoding latency and a high number of decoding failures. In this paper, a convergence-optimized structure for variable nodes is proposed that is able to overcome these issues. As a result, the throughput for the proposed decoder is 20.5Gb/s, which is 101% higher than the original counter-based decoder presented in the previous literature.

In this paper a hardware oriented integer motion estimation (IME) algorithm is proposed. The algorithm put forward to divide the largest coding unit (LCU) into four motion vector (MV) prediction cluster. Each cluster has a separate MV as the start for search window center. Then the best matched MV can be searched in a small size search window. All PUs in one quarter LCU sharing the same reference block save the bandwidth cost of loading reference block to the chip largely. In addition, the sum of absolute difference (SAD) value calculation for all the PUs in a quarter LCU are also shared, actually, only once calculation process is needed for all the PUs' distortion in it. Then, the algorithm is evaluated in the HEVC test model (HM-11.0), the results show that it only introduced 0.85% BDBR loss.

The latest video coding standard high-efficiency video coding (HEVC) provides 50% improvement in coding efficiency compared to H.264/AVC to meet the rising demands for video streaming, better video quality, and higher resolution. The deblocking filter (DF) and sample adaptive offset (SAO) play an important role in the HEVC encoder, and the SAO is newly adopted in HEVC. Due to the high throughput requirement in the video encoder, design challenges such as data dependence, external memory traffic, and on-chip memory area become even more critical. To solve these problems, we first propose an interlacing memory organization on the basis of quarter-LCU to resolve the data dependence between vertical and horizontal filtering of DF. The on-chip SRAM area is also reduced to about 25% on the basis of quarter-LCU scheme without throughput loss. We also propose a simplified bitrate estimation method of rate-distortion cost calculation to reduce the computational complexity in the mode decision of SAO. Our proposed hardware architecture of combined DF and SAO is designed for the HEVC intraencoder, and the proposed simplified bitrate estimation method of SAO can be applied to both intra- and intercoding. As a result, our design can support ultrahigh definition 7680 × 4320 at 40 f/s applications at merely 182 MHz working frequency. Total logic gate count is 103.3 K in 65 nm CMOS process.

Stereo matching is one of the key problems in computer vision. A large number of algorithms have been proposed but few of them achieve both high accuracy and short processing time on hardware. This paper presents a hardware-oriented stereo matching algorithm which is able to generate software-oriented-level results for 1920×1080 images at 48fps. Such performance prefigures new vistas of the applications of VLSI in stereo vision.

As the next generation of video coding standard, High Efficiency Video Coding (HEVC) aims to reduce 50% bit rates in comparison with previous video coding standards. In order to increase the Deblocking Filter (DBF) throughput, we propose a memory of ping-pong and interlacing VLSI architecture to prevent DBF from unnecessarily waiting for pixels in both vertical and horizontal, which only takes 435 cycles at worst to process a LCU of 64×64 pixels size. Based on the memory organization, a four stage pipeline with a PreFilter was proposed to eliminate the data dependence in the filter processing and makes it working on 318M possible. As a result, our design can support 8k×4k@90fps real-time applications with SMIC 0.13um technology at the cost of 62.9k gates.

Stochastic decoding can be applied to Low-Density Parity-Check codes in order to achieve high throughput with less area. However, most architectures suffer from large decoding latencies, due to the mechanism of stochastic computation. In this paper, three novel strategies, including the LUT-based initialization, the posterior-information-based hard decision and the Bit-Flipping-based post processing, are proposed in order to reduce decoding latency and hence improve throughput. For the standard IEEE 802.3an (2048, 1723) code, simulation indicates 75.7% reduction in average decoding cycles at 4.5 dB with satisfied bit error rate. Moreover, hardware implementation shows that the area of variable node units is reduced significantly in SMIC 65 nm technology.

This letter proposes a novel 1.5-D algorithm for multi-channel electroencephalogram (EEG) compression. The proposed algorithm only needs to perform 1-D Discrete Wavelet Transform (DWT) rather than the 2-D version employed by previous works, and thus it results in lower computational complexity and power dissipation. In this algorithm, a new 2-D arranging method that exploits correlations between different sub-bands is developed to concentrate the energy, which causes more efficient compression using No List Set Partitioning in Hierarchical Trees (NLSPIHT) algorithm. Experimental results demonstrate that the proposed algorithm outperforms 2-D NLSPIHT algorithm under the same compression ratio (CR) and it is slightly inferior to 2-D SPIHT algorithm in the near-lossless compression regime, but it can provide a better fidelity with respect to higher CRs.

Frame recompression is an efficient way to reduce the huge bandwidth of external memory for video encoder, especially for P/B frame compression. A novel algorithm, which is called mixed lossy and lossless (MLL) reference frame recompression, is proposed in this paper. The bandwidth reduction comes from two sources in our scheme, which differs from its previous designs and achieves a much higher compression ratio. First, it comes from pixel truncation. We use truncated pixels (PR) for integer motion estimation (IME) and acquire truncated residuals for factional motion estimation (FME) and motion compensation (MC). Because the pixel access of IME is much larger than FME and MC, it saves about 37.5% bandwidth under 3-b truncation. Second, embedded compression of PR helps to further reduce data. The truncated pixels in the first stage greatly help to achieve a higher compression ratio than current designs. From our experiments, 3-b truncated PR can be compressed to 15.4% of the original data size, while most current embedded compressions can only achieve around 50%. For PR compression, two methods are proposed: in-block prediction and small-value optimized variable length coding. With these experiments, the total bandwidth can be reduced to 25.5%. Our proposed MLL is hardware/software friendly and also fast IME algorithm friendly frame recompression scheme. It is more suitable to work together with the data-reuse strategy than the previous schemes, and the video quality degradation is controllable and negligible.

Pairings are attractive and competitive cryptographic primitives for establishing various novel and powerful information security schemes. This paper presents a flexible and high-performance processor for cryptographic pairings over pairing-friendly curves at high security levels. In this design, hardware for Fp2arithmetic is optimized to accelerate the pairing computation, and especially a combined modular multiplier, which implements (AB + CD) based on Montgomery method, is proposed. This combined multiplier has the data path delay close to that of a single multiplier implementing (AB) but saves 20% area cost compared with two single multipliers. The Design I of the proposed processor is the first fabricated chip for pairing cryptography. An improved version, Design II, is implemented using TSMC 65-nm CMOS technology and achieves the working frequency of 633 MHz after placing and routing. As demonstrated, the optimal ate pairings of 126- and 128-bit security can be computed by Design II in 0.521 and 0.554 ms, respectively. These results outperform the hardware implementations reported by previous works.

This brief proposes an ultralow-voltage four-read-port and two-write-port multiported register file with a novel architecture of read word-line sharing strategy for energy/area efficiency. Static read circuits and memory cells with nonminimum channel length are introduced to improve the ultralow-voltage performance. The chip of this register file is fabricated in 65-nm LP CMOS process and occupies the area of 0.019 mm$^{2}$ . Test results show that the minimum operation voltage is 320 mV with its corresponding max frequency 110 KHz. The minimum energy consumption is 0.94 pJ/cycle at the point of 400 mV, 850 KHz, corresponding to 0.15 fJ/port/bit/cycle after normalization. Compared with the state-of-the-art designs, it improves energy efficiency by 25% and saves the area by 58.7%.

The modular multiplication (MM) is a key operation in cryptographic algorithms, such as RSA and elliptic-curve cryptography. Multicore processor is a suitable platform to implement MM because of its flexibility, high performance, and energy-efficiency. In this paper, we propose a block-level parallel algorithm for MM with quotient pipelining and optimally map it on a network-on-chip-based multicore platform equipped with broadcasting mechanism. Aiming at highest performance, a theoretical speedup model for parallel MM is also developed for parameter exploration that optimizes task partitioning. Experimental results based on a multicore prototype show that compared with the sequential MM on single core, the parallel implementation proposed in this paper maximizes the speedup ratio with regard to given intercore communication latency.

This brief describes a new method to implement the single-port SRAM-based transpose memory for large size discrete cosine transform (DCT)/indiscrete cosine transform (IDCT) which are used in the latest video coding standard, such as high efficiency video coding. Instead of shift-register array or multiport SRAM, only single-port SRAM is used in the proposed design. A new diagonal data mapping scheme is proposed to reduce the number of SRAM banks used to implement the transpose memory. This design can be flexibly extended to support DCT/IDCT of different transform sizes and different data throughput rates. To support larger size DCT/IDCT, only the depth of SRAM needs to be increased. To support different data throughput rate, multiple SRAM banks are well organized according to the required throughput. Row access and column access can be perfectly supported under single port SRAM. The equivalent gate count per bit (EGC) of proposed approach is less than two, which is much more efficient than the previous method. It is suitable for real-time processing of the video with the resolution up to 1080P HD or even higher.

An efficient multi-rate Low-Density Parity-Check Convolutional Code decoder will be present in this paper. We will introduce layered decoding algorithm into LDPC-CC decoding. Simulation results shows that our method can achieve better performance than the original brief propagation algorithm with less processors. Besides a new ASIC architecture which adopt proposed algorithm and can support all code rate (1/2, 2/3, 3/4, 4/5) of the LDPC-CC code in IEEE 1901 is proposed. Based on SMIC 130 nm CMOS process, our decoder attaints a maximum throughput of 333.3 Mb/s at 200 MHz. The core area is 3.55 mm2with 10 processors. The average power consumption is 262 mW at code rate 4/5 and 200 MHz. The VLSI result shows that our decoder is both memory efficient and area efficient.

The 3780-point FFT is a main component of the time domain synchronous OFDM (TDS-OFDM) system in the Chinese Digital Terrestrial Multimedia Broadcasting (DTMB) national standard. In this paper, we proposed a pure software solution for the 3780-point FFT on a multi-core processor to achieve high performance and high flexibility. A new 12-point FFT implementation is used to improve system performance significantly since it is one of the key modules in 3780-point FFT. Together with some other techniques such as optimized assembly code, this 3780-point FFT improves the throughput by 39.26% and reduces the number of instructions by 19.9% compared with the non-optimized method. The throughput achieves 13.595 Msamples/s and meets the requirement of DMBT standard.

In this paper, we present a routing algorithm based on the Time-Division-Multiplexer technique for routing table based Network-on-Chip (NoC) routers to decrease the demand of the system bandwidth while ensuring deadlock free. To fully use the communication resources of NoC — channels, banker algorithm is adopted to allocate and recycle the resources, and a weighted maze algorithm is utilized to determine if there is an available path for the current communication process. Experimental results show that the bandwidth requirement with the proposed algorithm decreases by 71.4% compared with the odd-even algorithm.

As the next generation standard of video coding, the High Efficiency Video Coding (HEVC) aims to provide significantly improved compression performance in comparison with all existing video coding standards. We propose a four-stage pipeline hardware architecture on a quarter-LCU basis of deblocking filter in HEVC. Coupled with the novel filter order, a memory interlacing technique is adopted to increase the throughput, which can access the data in the process of both vertical and horizontal filtering efficiently. As a result, our design can support 4K×2K (4096×2048) at 30 fps applications with merely 28 MHz working frequency.

A split-capacitor Vcm-based capacitor-switching scheme is proposed for successive approximation register (SAR) analog-to-digital converters (ADCs) to reduce the capacitor-switching energy. By rearranging the structure and procedure of the capacitive array, the scheme can save the capacitor-switching energy by about 92% than the conventional scheme with better monotonicity. Meanwhile, a two-segment DC offset correction scheme for the comparator is also proposed to meet the speed and accuracy requirements. These techniques are utilized in the design of a 10b 70MS/s SAR ADC in 65nm 1P9M CMOS technology. Measurement results show a peak signal-to-noise-and-distortion ratio (SNDR) of 53.2dB, while consuming 960μW from 1.2V supply. The figure of merit (FoM) is 36.8fJ/Conversion-step and the total active area is 220×220μm2.

This paper presents a k-band (18–26.5 GHz) high gain low noise amplifier (LNA) in 65-nm CMOS mixed signal process. The LNA has a peak gain of 20.46 dB at 22.45 GHz and a −3 dB bandwidth of 3.8 GHz. S11 of the chip is better than −11 dB and S22 better than −15 dB across the band. The measured smallest noise figure (NF) is 3.4 dB. The whole chip consumes 11mA current under 1.1V supply voltage and occupies an area of 710 μm × 540 μm.

The register file (RF) consumes a large portion of power and is often a hotspot in microprocessor. In this paper, we propose and exploit several approaches to reducing both read and write access frequency to RF to reduce its power consumption and power density. Asynchronously controlled read-isolation is inserted in D Stage to prevent unused RF read access, triggered by a custom designed local asynchronous clock network, without changing the pipeline architecture and critical path. Software-directed write-discarding adopts static speculation algorithms to exploit short-lived values and determine their lifetime, with architectural supports to discard unnecessary writeback. Our approaches reduce RF access frequency by 27% for read and 50% for write, respectively. Moreover, 37% of RF power is eliminated with negligible overhead in area and almost no impact on the performance.

The attacks such as Denial of Service (DoS) violate the security of Network-on-Chip (NoC) which emerges as a promising solution for multi-core system. In this paper, we explore the robustness of mesh-based NoC architecture under various flooding-based DoS attacks. Simulation results reveal that the robustness of NoC architecture can be correlated with parameters such as routing algorithm, the number and positions of attacked nodes. It indicates that deterministic routing algorithm xy will result in less performance degradation than using other four adaptive routing algorithms studied in this paper when the attack traffic rate is lower than 0.65. However, the opposite conclusion can be made if much higher attack traffic rate is used. The performance degradation would escalate with the increasing number of at-tacked nodes. Moreover, the locations of attacked nodes will have an impact on the degree of performance degradation. Last but not least, some design guidelines for NoC against DoS attacks are proposed.

Low-power design has become a key technology for battery-power biomedical devices in Wireless Body Area Network. In order to meet the requirement of low-power dissipation for electrocardiogram related applications, a down-sampling QRS complex detection algorithm is proposed. Based on Wavelet Transform (WT), this letter characterizes the energy distribution of QRS complex corresponding to the frequency band of WT. Then this letter details for the first time the process of down-sampled filter design, and presents the time and frequency response of the filter. The algorithm is evaluated in fixed point on MIT-BIH and QT database. Compared with other existing results, our work reduces the power dissipation by 23%, 61%, and 72% for 1 ×, 2 ×, and 3 × down-sampling rate, respectively, while maintaining almost constant detection performance.

In this paper, a novel technique is proposed to address the joint sampling timing acquisition for baseband and broadband power-line communication (BB-PLC) systems using Orthogonal-Frequency-Division-Multiplexing (OFDM), including the sampling phase offset (SPO) and the sampling clock offset (SCO). Under pairwise correlation and joint Gaussian assumption of received signals in frequency domain, an approximated form of the log-likelihood function is derived. Instead of a high complexity two-dimension grid-search on the likelihood function, a five-step method is employed for accurate estimations. Several variants are presented in the same framework with different complexities. Unlike conventional pilot-assisted schemes using the extra phase rotations within one OFDM block, the proposed technique turns to the phase rotations between adjacent OFDM blocks. Analytical expressions of the variances and biases are derived. Extensive simulation results indicate significant performance improvements over conventional schemes. Additionally, effects of several noise models including non-Gaussianity, cyclo-stationarity, and temporal correlation are analyzed and simulated. Robustness of the proposed technique against violation of the joint Gaussian assumption is also verified by simulations.

Montgomery multiplication is the kernel operation in public key ciphers. Aiming at parallel implementation of Montgomery multiplication, this brief presents an improved task partitioning of the Montgomery multiplication algorithm for the multicore platform with area-efficient processors. Several multicore platforms are designed to verify the efficiency of parallelization. The fastest platform takes 3460 cycles to finish a 1024-b Montgomery multiplication, which is six times faster than a single MIPS processor and three times faster than the pSHS parallelization based on a platform with eight MicroBlaze cores.

A highly-parallel LDPC decoder architecture for 10Gbase-T applications is designed in this paper. Firstly, we reduce the routing complexity and corresponding power consumption by the proposed decoder architecture based on single routing networks. Secondly, the proposed architecture is designed with pipelined layered scheduling and multi-block parallel decoding, which improves operation speed and removes pipeline stalls in conventional highly-parallel layered scheduling. Thirdly, we trade off between hardware cost and throughput by a digit-serial data-path. Fourthly, an efficient early-termination circuit suitable for layered decoding is designed. The decoder is implemented in 130nm 1P8M CMOS process. The core area is 18.4mm2with 14% reduction, and the decoding throughput is 9.48Gbps operating at 278MHz and 5 iterations. The tested power consumption is 774mW at 1.2V and 80MHz.

Intra prediction is the most important technology in H.264/AVC intra frame encoder. But there is extremely complicated data dependency and an immense amount of computation in intra prediction process. In order to meet the requirements of real-time coding and avoid hardware waste, this paper presents a parallel and high efficient H.264/AVC intra prediction architecture which targets high-resolution (e.g. 4k×2k) video encoding applications. In this architecture, the optimized intra 4×4 prediction engine can process sixteen pixels in parallel at a slightly higher hardware cost (compared to the previous four-pixel parallel architecture). The intra 16×16 prediction engine works in parallel with intra 4×4 prediction engine. It reuses the adder-tree of Sum of Absolute Transformed Difference (SATD) generator. Moreover, in order to reduce the data-dependency in intra 4×4 reconstruction loop, a block-level and mode-level co-reordering strategy is proposed. Therefore, the performance bottleneck of H.264/AVC intra encoding can be alleviated to a great extent. The proposed architecture supports full-mode intra prediction for H.264/AVC baseline, main and extended profiles. It takes only 163 cycles to complete the intra prediction process of one macroblock (MB). This design is synthesized with a SMIC 0.13µm CMOS cell library. The result shows that it takes 61k gates and can run at 215MHz, supporting real-time encoding of 4k×2k@40fps video sequences.

This paper describes baseband SoC implementation of China Mobile Multimedia Broadcasting (CMMB) receiver, which integrates analog to digital (ADC), physical layer (PHY) baseband processor and medium access control (MAC) processor in single silicon wafer. MAC functions are fully implemented by firmware on an embedded 32-bit RISC-based processor. In addition, several power management techniques are utilized to reduce the power consumption of baseband SoC. The baseband SoC was successfully fabricated in 0.13µm one-poly six-metal (1P6M) CMOS process. Both analog and digital circuits are integrated on 4.8×4.8 mm2die consuming 60mW total power dissipation under 1.2V and 3.3V supplies. The experiment results reveal the proposed baseband SoC has excellent performance under the multipath channels.

4 or 8-point IDCT are widely used in traditional video coding standards. However larger size (16/32-point) IDCT has been proposed in the next generation video standard such as HEVC. To fulfill this requirement, this work proposes a fast computational algorithm of large size integer IDCT. A unified VLSI architecture for 4/8/16/32-point integer IDCT is also proposed accordingly. It can support the following video standards: MPEG-2/4, H.264, AVS, VC-1 and HEVC. Multiplier less MCM (Multiple Constant Multiplication) is used for 4/8-point IDCT. The regular multipliers and sharing technique are used for 16/32-point IDCT. The transpose memory uses SRAM instead of the traditional register array in order to further reduce the hardware overhead. It can support real-time decoding of 4K×2K (4096×2048) 30fps video sequence at 191MHz working frequency, with 93K gate count and 18944-bit SRAM. We suggest a normalized criterion called design efficiency to compare with previous works. It shows that this design is 31% more efficient than previous work.

In this paper, an improved algorithm of coarse synchronization in the downlink of 3GPP LTE system is presented. This new algorithm can reduce the MSE (mean square error) of detected fractional carrier frequency offset (FCFO) by an order of magnitude and improve the accuracy rate of start point estimation by near 80 percent when SNR equals 0 in contrast with conventional coarse synchronization algorithms, such as ML, MMSE, S&C and MC. The simulation result for the proposed algorithm is presented in comparison with the conventional algorithms.

Performance is one of the most important targets in MPSoC design, and it is affected by a lot of factors, such as area, yield, application, and lifetime. Based on the performance, yield and lifetime reliability modeling and analysis of MPSoC, this work proposes a metric directing how to choose the granularity of MPSoC at high level design in order to obtain high performance when yield and lifetime reliability are considered. The results show that, with the given area (300mm2) and certain applications, the optimal performance is obtained at 3×3 mesh, and optimal design becomes 4×4 mesh when yield is considered, and it will prefer 5×5 mesh or 6×6 mesh when lifetime reliability is further considered.

As an error correction code, Low Density Parity Check (LDPC) code has been widely used in various communication standards such as WiMAX and DVB-S2. But these continuously-evolving communication standards and the high development cost and low-flexibility of hardwired ASIC solutions have pushed LDPC researchers to turn to more cost-efficient and flexible implementation, and thus the multi-core processor based implementation of LDPC decoder is gaining increasing attention in the last few years. However, the performance of the multi-core processor based implementation is far below the hardwired ASICs, with one of the key reasons that the cost of communication between processors is very high. Three approaches are proposed in this paper to reduce the communication cost, including: optimized algorithm partitioning to reduce communication traffic, utilizing imbalanced communication between tasks to optimize mapping and reduce overall communication distance, and simplified data sending-receiving mechanism to reduce the cost of identifying received data. By using these approaches, the communication time of the proposed implementation of LDPC decoder only accounts for 12.2% of total decoding time, which generally occupies 50% decoding time in the previously reported LDPC decoders on multi-core processors. And our work can achieve better throughput performance under the same hardware condition compared with other state-of-the-art works.

This paper presents a high performance VLSI design of Context-Based Adaptive Variable Length-Coding (CAVLC) for 4096×2160p@60fps H.264/AVC encoder. A parallel architecture is proposed to make the scan and encode stage work simultaneously. Four coefficients are scanned in parallel, and four Levels and Run_before are coded in parallel. From experimental results, only 120 cycles at most are needed to process one macroblock (MB), which reduce more than 50% cycles compare to state-of-the-art designs. The hardware implementation results show that the proposed design achieves real-time encoding at 250 MHz and the hardware cost is about 32k gates.

Network-on-Chip (NoC) architecture is drawing intensive attention since it promises to maintain high performance in handling complex communication issues as the number of on-chip components increases. Mapping a given application onto the multi-core processors on NoC to obtain a high performance is a significant challenge. In this paper, we propose an optimized branch-and-bound (B&B) mapping algorithm to reduce the communication energy or improve the mapping efficiency by binding the tasks together when they have a large communication volume. Experimental results show that the proposed algorithm can achieve high performance in a short time compared with the traditional algorithm. For example, when mapping 64 tasks onto an 8×8 NoC system, with the approximate run time, 14.72% and 64.11% average energy consumption is saved compared with the original B&B and simulated annealing (SA) algorithms, respectively.

This paper presents an area efficient decoder architecture that supports both perfectly structured and not perfectly structured LDPC codes. To verify our architecture, an area-efficient LDPC decoder that supports both China Multimedia Mobile Broadcasting (CMMB) and Digital Terrestrial/ Television Multimedia Broadcasting (DTMB) standards is developed. A solution is proposed to avoid memory access conflict problem caused by TDMP algorithm. The main timing schedule is arranged carefully to handle the operations of our solution while avoiding much additional hardware consumption. We also optimize the extrinsic message storing strategy to reduce the memory bits needed. Besides the extrinsic message recover and the accumulate operation are merged together. Based on SMIC 0.13 um standard CMOS process, the core area of the decoder is only 4.75 mm2and the maximum operating clock frequency is 200 MHz. With 5 iterations, the estimated average power consumption is 48.4 mW at 25 MHz for CMMB and 130.9 mW at 50 MHz for DTMB with 1.2V supply.

An energy-efficient programmable LDPC decoder is proposed for WiMax and Wi-Fi applications. The proposed decoder is designed with overlapped processing units, flexible message passing network and medium-grain partitioned memories to achieve flexibility, area reduction, and energy efficiency. The decoder can be programmed by host processor with several special-purpose micro-instructions. Thus, various operation modes can be reconfigured. Fabricated in SMIC 0.13μm 1P8M CMOS process, the chip occupies 4.32 mm2with core area 2.97 mm2, and consumes 170mW with a throughput of 302Mb/s when operating at 145MHz and 1.2V.

This paper presents a reconfigurable and deadlock- free routing (RDR) algorithm. It can be reconfigured to adapt to the modification of the topology due to faulty routers. It is evaluated from the point of view of performance penalty under various fault patterns. Meanwhile deadlock-freedom and reconfigure mechanism issues are addressed. Fault-tolerance capability, re-configurability and scalability are further evaluated and compared to several other routing algorithms.

A novel channel estimation scheme is presented to combat long echo and high Doppler shift for Chinese digital television terrestrial broadcasting (DTTB) system. With this method, fast fading channel with Doppler shift about 200Hz can be well equalized even when OdB echo at 31.8us exists with head length 420, other modes likes 595 and 945 are also supported. Simulation results are given under Chinese DTTB standard to demonstrate the performance of the algorithm. This method can also be adopted to cyclic padded (CP) or zero padded (ZP) OFDM systems and single carrier ones.

This paper presents a multi-core processor with globally asynchronous locally synchronous (GALS) clocking style designed to achieve soft error tolerance for stream DSP applications, and to maintain system throughput energy efficiently. Each processor in the chip can be combined with one of its neighbor processors to run the same programs and their results are equivalence checked to detect the soft error occurrence. When error occurs in some processor, the program in that processor (not the whole chip) is re-executed from the saved state to recover from the error. Due to the programming model of stream DSP applications, each processor can be isolated by FIFOs in the proposed multi-core processors, and fault detection and recovery can be done with low overhead. Furthermore, the GALS clocking style allows adjusting the frequency of the processors hit by a soft error-not the frequency of the whole chip-to maintain the system throughput, which results high energy efficiency.

Adaptive Block-size Transform (ABT) has been added to H.264/AVC standard with the Fidelity Range Extension. In this paper, we apply this ABT concept to our FME design and propose a full-mode FME architecture based on 8×8/4×4 adaptive Hadamard Transform. This technique can avoid unifying all variable block-size blocks into 4×4-size blocks and improve the encoding performance. We also exploit the linearity of Hadamard Transform in quarter-pel refinement and decrease the cycles caused by the second long search process. In architecture level, we employ two interpolating engines that can support 8-pel and 4-pel input to time-share one SATD (Sum of Absolute Hadamard Transform) Generator. These strategies can increase parallelism and reduce the cycles efficiently. Besides, this design can support full modes, which guarantees the encoding performance. Experimental results show that our design can achieve real-time processing for QFHD@30fps at the operation frequency of 320MHz with 444.6K gates hardware.

This paper presents a hardware-efficient and high-throughput quantization implementation for H.264/AVC high profiles encoder. The constant multiplication in quantization is accomplished by time-multiplexed multiple-constant multipliers (MUX-MCM). By rational pipeline decision, the proposed design manages to achieve a high throughput at a low area cost. Synthesized with SMIC0.18µm technology, the proposed design reaches a maximum operating frequency of 250Mhz with a throughput of 1Gpixels/sec at the hardware cost of 28.56 Kgates.

A fully-overlapped multi-mode QC-LDPC decoder architecture, adopting improved TDMP algorithm, is presented in this paper. With symmetrical four-stage pipelining, block column and row permutations, nonzero sub-matrix reordering, sum memory odd-even partition, and read-write bypass, two phases are fully overlapped and each phase scans nonzero sub-matrices one by one in block row-wise order without access conflicts to sum memories. The sum memories store not only variable node sums but also prior messages. In this case, it saves an additional FIFO of 13 440 bits. The decoder attains 248-287 Mb/s at 150 MHz and 15 iterations.

In this paper a programmable and area-efficient decoder architecture supporting two main stream decoding algorithms for any Block-LDPC codes is presented. The novel decoder can be configured to decode in either TPMP or TDMP decoding mode according to different Block-LDPC codes. To verify our proposed architecture, a flexible LDPC decoder which supports IEEE 802.16e is implemented using a 0.13um CMOS process with a total area of 6.3 mm2 and maximum clock frequency of 260 MHz. The estimated comsumption is 270 mW when operates at 125 MHz and 1.2V supply.

In this paper, we present a novel 128/256-point FFT/ IFFT processor for the applications in IEEE 802.16e based on MIMO-OFDM. The pipeline FFT architecture is proposed to efficiently deal with 1-4 multiple data sequences, and increase the throughput. Furthermore, less hardware complexity is needed in our design compared with conventional individual parallel approach. The signal-to-quantization noise ratio (SQNR) is 42.7 dB. The proposed FFT has been designed in 0.13 μm technology with the core size of 1.470 × 1.469 mm2.

Computing design has been moving to multi-core or many-core domain and Network-on-chip (NoC) is upcoming. However, manufacturing defects and hard malfunction are inevitable, and fault-tolerant routing algorithm is important to provide the required communication in spite of failures. The proposed algorithm, referred to as scalable and fault-tolerant distributed routing (SFDR), partitions the system into nine regions using the concept of divide-and-conquer. Each region guarantees fault-tolerance of one's own area and the whole system still works no matter where the fault node locates. The novel routing algorithm has excellent scalability with hardware cost keeping constant independent of system size. The router has been synthesized using SMIC 0.13um CMOS process and there is almost no hardware overhead compared to Logic-Based Distributed Routing (LBDR) which is only partially fault-tolerant and hardware cost reduces up to 42% compared to table-based routing.

The quasi-cyclic low-density parity-check (QC-LDPC) codes are widely applied in digital broadcast and communication systems. However, the decoders are still difficult to be put into practice due to their large area and high power, especially in the wireless mobile devices. This paper presents an improved all-purpose multirate iterative decoder architecture for QC-LDPC codes, which can largely reduce their area and power. The architecture implements the normalized min-sum algorithm, rearranges the original two-phase message-passing flow, and adopts an efficient quantization method for the second minimum absolute values, an optimized storing scheme for the position indexes and signs, and an elaborate clock gating technique for substantive memories and registers. It is also configurable for any regular and irregular QC-LDPC codes, and can be easily tuned up to different code rates and code word lengths. The chip is fabricated in an SMIC 0.18- six-metal-layer standard CMOS technology. It attains a throughput of 104.5 Mb/s, and dissipates an average power of 486 mW at 125 MHz, and 15 decoding iterations. The core area is only 9.76 mm2. The chip has been applied into the China digital terrestrial/television multimedia broadcasting system.

A multi-task-oriented security processing architecture is presented in this paper. This architecture contains a host microprocessor and multiple security processors (SP). The SP could integrate dedicated Crypto-Engines, which provides functional extensibility. And the performance scalability and multi-task parallelism could be enhanced by increasing the number of SPs on system bus. It's demonstrated that this architecture greatly improves the system efficiency. A test chip is implemented based on SMIC 0.18 um standard CMOS technology, and its functionality is well verified.

A low-cost cryptographic processor for security embedded system is presented in this paper. The processor, without any assistance of dedicated cryptographic coprocessors, is scalable and very efficient for popular cryptographic algorithms such as RSA/ECC, AES, Hash, etc. Based on SMIC 0.18 um standard CMOS technology, the core circuit of the test chip has only about 32 k gates, and a max frequency of 200 MHz, under which the 1024-bit RSA algorithm takes only 150 ms and the throughout of AES reaches 256 Mbits/s.

A full-custom design of AES SubByte module based on sense amplifier based logic is proposed in this paper. Power consumption of this design is independent of both value and sequence of data. Therefore this design is resistant to power analysis attack. This design is implemented using SMIC 0.18 um CMOS technology. Simulation results show that it can work at the frequency of 83.3 MHz, and its total area is about 0.85 mm2. This design is suitable for application in the hardware implementation of symmetric-key cryptographic devices that have high security demand.

In this paper, we present an optimal frame synchronization scheme for DVB-S2 system. The scheme is based on differential detection and non-threshold peak search algorithm to achieve frame synchronization. By further analyzing the structure of the Physical Layer Header (PLHEADER) that consists of Start of Frame (SOF) and Physical Layer Signalling Code (PLSC), we find some useful properties that can enhance the frame synchronization and reduce the complexity of its implementation. We also introduce some optimizations into the algorithm. Especially, the modifications made on the peak search algorithm improve the overall performance of the frame synchronization. The experimental results show that the optimal frame synchronization can be achieved under large carrier frequency offset (as large as 5MHz at 25MSps) and low SNR threshold of −2.3dB. Compared with previously proposed approaches, the scheme described in this paper takes less time to acquire frame synchronization and seems to be more robust.

In impulse-radio ultra-wide band (IR-UWB) communications, even a small timing error would lead to a serious degradation in system performance in the multi-path circumstance. To deal with the challenge, a novel hybrid synchronous sampling timing locked loop is proposed in this paper. Timing error detector, the crucial unit of TLL, is realized based on a maximum-likelihood estimation method. Both mathematical analysis and simulations on S-Curve and timing error variance indicate a high performance of the proposed TLL at low signal to noise rate. It is also demonstrated that in the environment of IEEE 802.15.3a Multi-path channels, the proposed TLL improves system bit error rate (BER) performance by two orders of magnitude when the timing jitters are around half a pulse duration. Furthermore, it is observed through simulations that five figures selective Rake receiver is advisable for a satisfactory system BER performance.

A SoC design for applications of OMA DRM 2 Agent in mobile phones is presented in this paper, which has been verified by Altera Stratix EP1S80B956C6 FPGA development board. Several design aspects, which include an embedded 32-bits RISC CPU and AMBA™ bus system, a DRM Agent accelerator, a high-performance TRNG, several interfaces and reasonable hardware/software partition, making it very efficient for the OMA DRM 2 application. Based on SMIC 0.25μm standard CMOS technology, the proposed SoC platform can work under the frequency of about 76MHz, and the core circuit is 112k gates, making it suitable for low-cost design. Besides, memory protection unit is added to enhance the security. Therefore, the proposed SoC platform has a fine potential in application.

In this paper, a novel synchronization method for IR-UWB systems is proposed. Integrate-and-dump operations at the symbol rate are done over the product of the received signal and its Ts-delayed replica. The relative proportion of the two parts constituting these symbol-rate samples, termed the "energy-proportion" in this paper, makes it possible to achieve frame-level synchronization in a fast and reliable way. Two propositions were developed to estimate the energy-proportion in both nondata-aided (NDA) and data-aided (DA) modes, and a training pattern was designed for the DA mode. Simulations indicate that the DA proposition outperforms NDA in terms of both mean square error and bit-error rate. This new synchronization method eliminates the slide-correlating operation required in most existing alternatives, and thus considerably shortens the synchronization time and reduces the complexity.

A platform-based SoC named as Firebird is presented in this paper, which is used for the applications of information security. Several design aspects, which includes the embedded 32-bit RISC CPU and AMBA controller, the reconfigurable and scalable public-key crypto-coprocessor, high-performance TRNG and several low-power schemes, make Firebird very efficient for the client-end applications of information security. Also the test results of this prototype chip indicate that Firebird can work with all these features efficiently, and has some obvious advantages over other designs in the literatures.

This paper proposed a high-radix scalable Montgomery multiplier with the efficient data-path and half latency. By using new algorithm proposed by this paper, it achieves shorter critical path by calculating coefficient qYand qMin parallel. The algorithm can also provide half latency by changing pipeline dataflow through operands dynamic extending during calculation. This design can be used to accept any input precision up to the size of the on-chip memory. An ASIC implementation in 0.25 mun CMOS technology can perform 1024-bit RSA encryption with 390k bps under 180MHz frequency

Based on modified multiple-word radix-4 Montgomery algorithm and improved pipeline mechanism, an area efficient RSA crypto-processor is implemented, which supports reconfigurable keys up to 2048 bits. Based on 0.25mum standard CMOS technology, the new coprocessor achieves a 1024-bit encryption rate of 28Kbps at 180MHz and the core circuit without RAM contains 18,000 gates. The result shows that this processor is very suitable for area-constrained applications such as smart cards

A new elliptic curve cryptography (ECC processor is proposed in this paper, which supports Galois fields GF(p) and GF(2/sup n/) arithmetic for arbitrary prime numbers and irreducible polynomials by introducing a dual-field unified algorithm and data-path. To speed up the scalar multiplication, OJW (optimal joint weight) form is used to convert the integers to optimal signed-binary form on the fly, which is especially useful for the verifying operation of elliptic curve digital signature algorithm. Also in this paper, Montgomery multiplication and modular division algorithm are unified to achieve high area-efficiency and carry-save redundant form of the intermediate results is preserved to reduce the critical path delay. At the same time, the EC arithmetic is executed in an anti-attack form ensuring the proposed design against side-channel power attacks efficiently.

This paper presents a compact self-biased current-mode filter (CMF) PLL architecture, which uses relative ratio of charge-pump currents (Icp2/ |Icp2-Icp1|) to obtain a capacitor multiplier. Compatible with self-biased CMF, a modified charge pump switches structure is proposed to reduce phase offset and current activating time. The whole PLL has been designed and implemented in a 0.25 mum CMOS process. The simulated PLL provides the loop parameters almost independent of divider multiplication factor, and decreases the capacitance to 1/10 of conventional one, and the results also shows it reduces the acquisition time by a factor of about 3