This paper presents adaptive variation-and-error-resilient agent (AVERA), an approach to address the challenge of designing reliable systems in the presence of soft errors and variations. AVERA extends our previous built-in soft error resilience (BISER) approach by adding additional capabilities to support process variation diagnosis, degradation detection, and system adaptation, besides soft error correction. We also discuss open challenges for building variation-and-error-resilient systems.

We present two techniques for correcting radiation-induced soft errors in combinational logic - error correction using duplication, and error correction using time-shifted outputs. Simulation results show that both techniques reduce combinational logic soft error rate by more than an order of magnitude. Soft errors affecting sequential elements (latches and flip-flops) at combinational logic outputs are automatically corrected using these techniques

This paper presents an overview of the built-in soft error resilience (BISER) technique for correcting soft errors in latches, flip-flops and combinational logic. The BISER technique enables more than an order of magnitude reduction in chip-level error soft rate with minimal area impact, 6-10% chip-level power impact, and 1-5% performance impact (depending on whether combinational logic error correction is implemented or not). In comparison, several classical error-detection techniques introduce 40-100% power, performance and area overheads, and require significant efforts for designing and validating corresponding recovery mechanisms. Design trade-offs associated with the BISER technique and other existing soft error protection techniques are also analyzed

We present a soft-error-rate analysis (SERA) methodology for combinational and memory circuits. SERA is based on a modeling and analysis approach that employs a judicious mix of probability theory, circuit simulation, graph theory, and fault simulation. SERA achieves five orders of magnitude speedup over Monte Carlo-based simulation approaches with less than 5% error. Dependence of the soft-error rate (SER) of combinational logic circuits on a supply voltage, clock period, latching window, circuit topology, and input vector is explicitly captured and studied for a typical 0.18-$muhboxm$CMOS process. Results show that the SER of logic is a much stronger function of timing parameters than the supply voltage. Also, an SER peaking phenomenon in multipliers is observed where the center bits have an SER that are orders of magnitude greater than those of the LSBs and the MSBs. An increase of up to 25% in the SER for multiplier circuits of various sizes has been observed as technology scales from 0.18 to 0.13$muhboxm$.

This paper presents a built-in soft error resilience (BISER) technique for correcting radiation-induced soft errors in latches and flip-flops. The presented error-correcting latch and flip-flop designs are power efficient, introduce minimal speed penalty, and employ reuse of on-chip scan design-for-testability and design-for-debug resources to minimize area overheads. Circuit simulations using a sub-90-nm technology show that the presented designs achieve more than a 20-fold reduction in cell-level soft error rate (SER). Fault injection experiments conducted on a microprocessor model further demonstrate that chip-level SER improvement is tunable by selective placement of the presented error-correcting designs. When coupled with error correction code to protect in-pipeline memories, the BISER flip-flop design improves chip-level SER by 10 times over an unprotected pipeline with the flip-flops contributing an extra 7-10.5% in power. When only soft errors in flips-flops are considered, the BISER technique improves chip-level SER by 10 times with an increased power of 10.3%. The error correction mechanism is configurable (i.e., can be turned on or off) which enables the use of the presented techniques for designs that can target multiple applications with a wide range of reliability requirements

Radiation induced soft errors in flip-flops, latches and combinational logic circuits, also called logic soft errors, pose a major challenge in the design of robust platforms for enterprise computing and networking applications. Associated power and performance overheads are major barriers to the adoption of classical fault-tolerance techniques to protect such systems from soft errors. Design-for-functional-test and debug resources can be reused for built-in soft error resilience during normal system operation resulting in more than an order of magnitude reduction in the undetected soft error rate. This design technique has negligible area and speed penalties, and the chip-level power penalty is significantly smaller compared to classical fault-tolerance techniques.

We present a soft error rate analysis (SERA) methodology for combinational and memory circuits. SERA is based on a modeling and analysis-based approach that employs a judicious mix of probability theory, circuit simulation, graph theory and fault simulation. SERA achieves five orders of magnitude speed-up over Monte Carlo based simulation approaches with less than 5% error. Dependence of soft error rate (SER) of combinational circuits on supply voltage, clock period, latching window, circuit topology, and input vector values are explicitly captured and studied for a typical 0.18 /spl mu/m CMOS process. Results show that the SER of logic is a much stronger function of timing parameters than the supply voltage. Also, an "SER peaking" phenomenon in multipliers is observed where the center bits have an SER that is in order of magnitude greater than that of LSBs and MSBs.