Memory and logic devices in processing of information employ deterministically correct binary manipulation by a large ensemble of small devices. Smallest critical dimensions on a chip are in nanometers and the largest are in centimeters. Within the device themselves, 3-D, 2-D, 1-D, or even 0-D effects and their properties may be employed. This integrated circuit ensemble in its present form manipulates the information for an informational objective under constraints, among many, of energy, time, and absolute correctness. Four example sets illustrating the consequences of this approach arising from statistical, thermodynamic, quantum-mechanic, and information mechanic considerations are analyzed. The first illustrates the implication on a minimum in energy in any binary state change of >250kBT. The second illustrates the connection between the nature of memory mechanism to the fluctuations and their guiding statistics that lead to the variability and errors. The third illustrates the limits arising in dissipative access due to dimensionality change. The fourth illustrates the interaction between fluctuations and on-chip signal transmission and manipulation with their resultant constraints. We tie this analysis to devices aimed at subthreshold conduction control, the change to on-state and low voltage operations. These examples illustrate the constraints placed on the reductive march through the connections of scales that leave the electronic ensemble nearly nine orders of magnitude off the thermodynamic capacity in information efficiency. A naturally probabilistic Bayesian computation example is provided as an alternative toward achieving efficiency.

Numerous computing applications can tolerate low error rates. In such applications, inexact approaches provide the ability to achieve significantly lower power. This work demonstrates the power-error trade-offs that can be achieved. Using probabilistic modeling in sub-50-nm silicon transistor technology, the relationship between statistical uncertainties and errors are elucidated for different configurations and topologies and the trade-offs quantified. Gate-level implementation of the probabilistic CMOS logic is validated by circuit simulations of a commercial 45-nm SOI CMOS process technology. Using a practical ALU architecture where voltages can be scaled from most significant to least significant bit blocks as an example, the potential benefits of this technique are shown. A calculation error of 10 −6 , an error rate quite tolerable for many computational tasks, is shown to be possible with a total power reduction of more than 40%.