Demo Data from VLDB 2026 / reviewers in the wild / expert
Daniel L. Slotnick
dblp:73/2785
· DBLP profile ↗
3ranked-venue papers
2as first author
0since 2021 · last 1968
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Parallel and multicore computing · 43% Processor architecture and microarchitecture · 29% Reconfigurable computing and FPGAs · 29% | |
| Software engineering, system software, and programming languages
1 paper |
Operating systems · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Parallel and multicore computing
parallel architecture |
0.0 | 1 | 1968 | The ILLIAC IV Computer · IEEE Trans. Computers 1968 |
Reconfigurable computing and FPGAs › coarse-grained reconfigurable architecture
processing element array |
0.0 | 1 | 1968 | The ILLIAC IV Computer · IEEE Trans. Computers 1968 |
Processor architecture and microarchitecture
SIMD |
0.0 | 1 | 1968 | The ILLIAC IV Computer · IEEE Trans. Computers 1968 |
Parallel and multicore computing › concurrent system
multiprogramming |
0.0 | 1 | 1963 | The Computer System Issue · IEEE Trans. Electron. Comput. 1963 |
Operating systems › resource management › process management
CPU scheduling |
0.0 | 1 | 1963 | The Computer System Issue · IEEE Trans. Electron. Comput. 1963 |
Methods — techniques the papers use, named apart from their topics
supervisor program · 0.0hardware support · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1968 | The ILLIAC IV ComputerabstractAbstract—The structure of ILLIAC IV, a parallel-array computer containing 256 processing elements, is described. Special features include multiarray processing, multiprecision arithmetic, and fast data-routing interconnections. Individual processing elements execute 4×106instructions per second to yield an effective rate of 109 operations per second. George H. Barnes, Richard M. Brown, Maso Kato, David J. Kuck, Daniel L. Slotnick, Richard A. Stokes |
IEEE Trans. Computers | 5 |
| 1963 | The Computer System IssueabstractThe ZAM-41 is a medium-sized, high-speed, parallel, binary computer with the word length of 24 bits and the internal storage capacity from 8192 to 32,768 words. It is destined mainly for data processing, but it may also be used for scientific computations and for real-time control. The full effect of multiprogramming has been obtained on the above computer by means of a small amount of hardware and an appropriate supervisor program. The problem of mutual interference of concurrently performed programs has been particularly taken into account. Daniel L. Slotnick |
IEEE Trans. Electron. Comput. | 1 |
| 1963 | Comments on H.J. Heijf's Review of "The SOLOMON Computer
Daniel L. Slotnick, W. Carl Borck, Robert C. McReynolds |
IEEE Trans. Electron. Comput. | 1 |