This paper presents a new inter-domain multicast protocol, the global multicast routing protocol (GMRP), that has the potential to be highly scalable and efficient, and, at the same time is simple to implement. GMRP minimizes signaling traffic, optimizes bandwidth use and remains unaffected by the group dynamics. We show that GMRP performs better when compared to hierarchical distance vector multicast routing protocol (HDVMRP).

One of the main problems with wireless networks is the tracking of mobile units (MU) as they move from one geographic position to another. This tracking of MUs is called location management. Network signaling protocols and databases are required to track each MU. Current location management protocols, such as ANSI-41 (IS-41), provides the means necessary to track MUs. Unfortunately, IS-41 has several drawbacks. Many location management protocols have been proposed to improve upon IS-41. However, along with IS-41, these proposed protocols also have limitations. Proximity location management (PLM) is being introduced to alleviate the limitations associated with these location management protocols.

We present the split input sunshine switch, a new ATM switch architecture based on the sunshine switch, which utilizes two distinct input fabrics, primary and secondary, within a sunshine switch architecture. The primary input fabric is sized at the desired size, N/spl times/N, and the secondary switch is sized at N/z /spl times/ N/z, where z is a non-zero power of two. The introduction of the secondary input fabric allows a portion of the primary input fabric's input lines to be used to handle recirculating cells. For medium and large switch sizes, the hardware requirements of this new architecture is shown to be less than that of the original sunshine design for the same quality of service. Computer simulations have been performed on the sunshine switch and the split input sunshine switch in order to select design parameters and compare performance.

In this paper, we present a new implementation of the fast VLSI-efficient self-routing N/spl times/N permutation network proposed by Cam and Fortes, which requires only about half as much hardware and has a lower latency. Cam and Fortes' implementation uses Cormen and Leiserson's hyperconcentrators, which can route only active inputs. The reduction in hardware is achieved by modifying Cormen and Leiserson's hyperconcentrator to route active, as well as inactive, inputs to the output. This modification allows us to reduce the number of hyperconcentrators needed in the permutation network by 50 percent and eliminate the interstage interconnection networks, making the permutation network faster by log/sub 2/N bits.