The introduction of multiple transform types in the Versatile Video Coding (VVC) standard has yielded notable encoding gains but also imposed considerable computational burdens. Existing transform circuits of different types are typically implemented separately due to their independence, leading to substantial hardware overhead. To address this, we explore the relationship between Discrete Cosine Transform Type-2 (DCT2) and Discrete Sine Transform Type-7 (DST7) matrices and reveal a prominent diagonal aggregation phenomenon in their transfer matrix. Based on this insight, the least-squares method is applied to optimize the transfer matrix sparsity, achieving a high-precision, low-cost approximate conversion from DCT2 to DST7. Furthermore, we optimize DCT2 computation by proposing an elaborate matrix decomposition approach that allows a lightweight shift-adder unit to efficiently generate all required product terms across varying sizes. Leveraging these algorithmic optimizations, we implement a highly reusable and area-efficient approximate transform accelerator that supports sizes from 4 to 32 points and accommodates three types in VVC. Experimental results demonstrate that the proposed accelerator achieves over 44% reduction in circuit resource consumption with negligible BD-BR performance loss of just $\mathbf{0. 5 3 \%}$, maintaining processing capabilities up to $8 K \text{@} 57 \mathrm{fps}$.

This article introduces a novel power amplifier integrated active antenna (PAIAA) with increased efficiency that integrates a Class-$F {^{-}1 }$Gallium Nitride (GaN) power amplifier (PA) and a stub-loaded wide slot antenna (SLSA) for wireless power transmission (WPT) applications. Unlike conventional PA integrated active antennas in which antennas and PAs are separately matched to 50 ohms, the input impedance of the SLSA is meticulously engineered to match the fundamental impedance and modulate harmonic impedances of the GaN transistor by optimizing the dimensions of the SLSA's stubs. This approach eliminates the output matching network (OMN), the PA's harmonic modulation network (HMN), and the antenna's input matching network (IMN), which typically incur unavoidable insertion loss but are essential for conventional Class-$F {^{-}1 }$PAs and antennas. Consequently, it enhances the power-added efficiency (PAE) within the 3.3–3.8-GHz range and reduces the overall size of the PA integrated active antenna. Thanks to the extended design freedom offered by SLSA, precise impedance values can be achieved across a broader frequency range, resulting in increased efficiency across a larger spectrum. In addition, an innovative insertion loss measurement method for impedance matching network with a non-50-$\Omega $port is introduced to accurately measure the Class-$F {^{-}1 }$PA's PAE incorporated in the proposed PAIAA. The measured PAIAA demonstrates a peak PAE of 70.1%, surpassing the performances of reported integrated active antennas. The measured effective isotropic radiated power (EIRP) of the proposed PAIAA is 44.52 dBm. A conventional PA-antenna design, where an antenna and a Class-$F {^{-}1 }$PA are separately matched to$50~\Omega $and simply cascaded, is also designed and measured as a contrast, whose measured peak PAE and EIRP of the conventional design are only 61.5% and 43.9 dBm, respectively. The proposed PAIAA, with its increased efficiency, can be practically utilized for WPT applications in the Internet of Things (IoT), where efficiency performance is critical.

The introduction of multiple transform types into the Versatile Video Coding (VVC) standard has yielded notable encoding gains but also resulted in substantial computational burdens, posing two critical challenges for hardware implementation: fast kernel selection and efficient transform computation design. Existing studies typically address these challenges in isolation, lacking a holistic solution for VVC transform coding. In this paper, we presents a groundbreaking transform accelerator that unifies transform kernel selection and multiple transform circuit within a single framework. In terms of algorithms, driven by mechanistic analysis, we propose a decision tree-based kernel selection algorithm that ensures both high decision accuracy and computational efficiency. Additionally, we design a transfer matrix-based approximation algorithm for Discrete Sine Transform Type-7 and a matrix decomposition-based improved computation for Discrete Cosine Transform Type-2, significantly reducing the computational complexity. On the hardware front, we implement a high-precision and area-efficient transform accelerator, which integrates highly pipelined kernel selection and transform computation architectures. With multiple reuse and parallelism strategies, the accelerator demonstrates substantial resource efficiency advantages. Experimental results reveal that the proposed accelerator achieves a circuit resource reduction of over 44% with a slight performance degradation, while maintaining processing capabilities up to 8K@57 fps. To the best of our knowledge, this is the first comprehensive hardware solution for VVC transform coding that jointly addresses the challenges of kernel selection and transform circuit design.

In recent years, fully-connected hybrid beamforming (FC-HBF) architecture has aroused widespread interest for millimeter wave (mmWave) massive multi-input multi-output (MIMO) communication systems. However, the FC-HBF structure suffers from significant linearity deterioration, limiting its applications in actual mmWave transmitters. To resolve this issue, an effective digital predistortion (DPD) method utilizing analytical multi-input behavioral models is proposed in this paper for linearizing the FC-HBF system. Based on the nonlinearity analysis and behavioral modeling of the array response, three analytical multi-input models are derived by embedding the priori beamforming information in the predistorter. The complexity of the proposed analytical models is significantly reduced compared to the state-of-the-art. Numerical simulations and experimental measurement are carried out on a$4\times 64$mmWave FC-HBF array and$2\times 16$quasi-test platform respectively to validate the performance of the proposed DPDs against the state-of-the-art DPDs, which show significant linearization abilities to compensate for the nonlinear distortions of beam signals. The proof-of-the-concept validations in this paper indicate that the proposed scheme is fully capable of linearizing an mmWave FC-HBF array.