Demo Data from VLDB 2026 / reviewers in the wild / expert
Peter N. Marinos
dblp:73/3672
· DBLP profile ↗
14ranked-venue papers
4as first author
0since 2021 · last 1996
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 11 · 4 first-authorSoftware engineering, systems software and programming languages · 2Artificial intelligence and machine learning · 1Human-computer interaction and ubiquitous computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
4 papers |
Distributed systems · 55% Performance modeling and evaluation · 20% Electronic design automation · 10% |
Topics — the 13 heaviest of 14, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Distributed systems
clock synchronization |
0.0 | 1 | 1988 | Synchronization of Fault-Tolerant Clocks in the Presence of Malicious Failures · IEEE Trans. Computers 1988 |
Distributed systems
fault tolerance |
0.0 | 1 | 1988 | Synchronization of Fault-Tolerant Clocks in the Presence of Malicious Failures · IEEE Trans. Computers 1988 |
Performance modeling and evaluation › simulation
architectural simulation |
0.0 | 1 | 1983 | An interactive simulation facility for the evaluation of shared-resource architectures (Parallel ARchitecture SIMulator - PARSIM) · DAC 1983 |
Performance modeling and evaluation
simulation |
0.0 | 1 | 1983 | An interactive simulation facility for the evaluation of shared-resource architectures (Parallel ARchitecture SIMulator - PARSIM) · DAC 1983 |
Distributed systems › fault tolerance
byzantine fault tolerance |
0.0 | 1 | 1988 | Synchronization of Fault-Tolerant Clocks in the Presence of Malicious Failures · IEEE Trans. Computers 1988 |
Distributed systems
consensus |
0.0 | 1 | 1988 | Synchronization of Fault-Tolerant Clocks in the Presence of Malicious Failures · IEEE Trans. Computers 1988 |
Electronic design automation
logic synthesis |
0.0 | 1 | 1977 | Programmable Array Realizations of Synchronous Sequential Machines · IEEE Trans. Computers 1977 |
Reconfigurable computing and FPGAs › reconfigurable architecture
programmable cellular arrays |
0.0 | 1 | 1977 | Programmable Array Realizations of Synchronous Sequential Machines · IEEE Trans. Computers 1977 |
Distributed systems › fault tolerance
fault detection and diagnosis |
0.0 | 1 | 1971 | Derivation of Minimal Complete Sets of Test-Input Sequences Using Boolean Differences · IEEE Trans. Computers 1971 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 1971 | Derivation of Minimal Complete Sets of Test-Input Sequences Using Boolean Differences · IEEE Trans. Computers 1971 |
Electronic design automation › hardware verification and test › test generation
test sequence generation |
0.0 | 1 | 1971 | Derivation of Minimal Complete Sets of Test-Input Sequences Using Boolean Differences · IEEE Trans. Computers 1971 |
Electronic design automation › logic synthesis
finite state machine synthesis |
0.0 | 1 | 1977 | Programmable Array Realizations of Synchronous Sequential Machines · IEEE Trans. Computers 1977 |
Electronic design automation › hardware verification and test › test generation
boolean difference |
0.0 | 1 | 1971 | Derivation of Minimal Complete Sets of Test-Input Sequences Using Boolean Differences · IEEE Trans. Computers 1971 |
Methods — techniques the papers use, named apart from their topics
simulation · 0.0hardware experimentation · 0.0averaging rule · 0.0parallel simulation · 0.0synthesis algorithm · 0.0k-out-of-n state assignment · 0.0boolean difference · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1996 | Unification of finite failure non-homogeneous Poisson process models through test coverageabstractA number of analytical software reliability models have been proposed for estimating the reliability growth of a software product. We present an Enhanced Non-Homogeneous Poisson Process (ENHPP) model and show that previously reported Non-Homogeneous Poisson Process (NHPP) based models, with bounded mean valve functions, are special cases of the ENHPP model. The ENHPP model differs from previous models in that it incorporates explicitly the time varying test coverage function in its analytical formulation, and provides for defective fault detection and test coverage during the testing and operational phases. The ENHPP model is validated using several available failure data sets. Swapna S. Gokhale, Teebu Philip, Peter N. Marinos, Kishor S. Trivedi |
ISSRE | 3 |
| 1996 | Important Milestones in Software Reliability Modeling
Swapna S. Gokhale, Peter N. Marinos, Kishor S. Trivedi |
SEKE | 2 |
| 1988 | The Non-Linear Feedback Shift-Register as a Built-In Self-Test (BIST) ResourceabstractProperties of nonlinear-feedback shift registers (NLFSRs), are studied and their suitability as built-in self-test (BIST) components in VLSI circuits is investigated. The feasibility is discussed of mapping fault-free circuit-under-test response to one of the least frequently occurring signatures within the signature space of the n-stage NLFSR. A number of illustrations are offered that justify the serious consideration of NLFSRs as components for use in BIST applications.> Peter N. Marinos |
ITC | 1 |
| 1988 | Design of a bus-monitor for real-time applications
Nick Kanopoulos, Peter N. Marinos |
Microprocess. Microprogramming | 2 |
| 1988 | Synchronization of Fault-Tolerant Clocks in the Presence of Malicious FailuresabstractThe problem of achieving global clock synchronization in fault-tolerant clocks by preventing so-called multiple cliques in the presence of malicious clock failures (i.e. clock failures that are perceived differently by different nonfaulty clocks) is addressed. A solution to the problem, referred to as the averaging rule, is developed, and its use is analytically justified using the notions of clock partitions and generalized clock partitions. Experimental characterization of the multiple cliques problem has been undertaken, and certain conditions that induce their occurrence in practical hardware implementation are identified. The effects of clock-receiver triggering variations and phase-detector operating range on the instantaneous frequencies of the clock modules are investigated. The efficacy of the averaging rule is established not only by analysis but also by means of simulations and experimentation with hardware clock implementations.> Nagesh Vasanthavada, Peter N. Marinos |
IEEE Trans. Computers | 2 |
| 1986 | Functional Testing of Microprocessor-like Architectures
Günhan Kildiran, Peter N. Marinos |
ITC | 2 |
| 1986 | Testing of Fault-Tolerant Clock Systems
Nagesh Vasanthavada, Peter N. Marinos, Gerald S. Mersten |
ITC | 2 |
| 1985 | An Operationally Efficient Scheme for Exhaustive Test-Pattern Generation Using Linear Codes
Nagesh Vasanthavada, Peter N. Marinos |
ITC | 2 |
| 1983 | An interactive simulation facility for the evaluation of shared-resource architectures (Parallel ARchitecture SIMulator - PARSIM)
John A. Board Jr., Peter N. Marinos |
DAC | 2 |
| 1977 | Programmable Array Realizations of Synchronous Sequential MachinesabstractCellular-array realizations of switching functions have been studied in order to take advantage of the many design possibilities offered by large-scale integration technology. This paper introduces a class of programmable cellular arrays that can be employed to realize arbitrary synchronous sequential machines. State assignments based upon k-out-of-m codes are employed to give rise to machine excitation and output equations in a consistent functional form suitable for implementation via a cellular structure. The proposed arrays are programmable, which makes possible the capability of re-configuring an array to realize different machines by electronically altering the function implemented by each cell of the array. A synthesis algorithm is presented that will allow the designer to program the array without explicitly deriving excitation and output functions. The synthesis technique is applicable to both Mealy and Moore machines with any number of inputs, outputs, and internal states, and utilizing either delay or trigger flip-flops. Edward W. Page, Peter N. Marinos |
IEEE Trans. Computers | 2 |
| 1976 | Author's Reply
Peter N. Marinos |
IEEE Trans. Computers | 1 |
| 1974 | Deterministic Acceptors of Regular Fuzzy LanguagesabstractThe one-to-one relationship between finite automata, regular (type-3) languages, and regular expressions is well known. This correspondence demonstrates the use of regular expressions for describing deterministically finite fuzzy automata and regular fuzzy languages, and introduces a normal form for the production of a regular fuzzy grammar when the ``max(min)'' rule is used. Michael G. Thomason, Peter N. Marinos |
IEEE Trans. Syst. Man Cybern. | 2 |
| 1971 | Derivation of Minimal Complete Sets of Test-Input Sequences Using Boolean DifferencesabstractThis paper deals with a fault detection and diagnosis technique based on Boolean differences. A brief review of the notion of a Boolean difference is presented, and the concept of partial Boolean difference is introduced. An algorithm for obtaining minimal, complete sets of test-input sequences based on the partial Boolean differences of a switching function is formulated, and illustrations demonstrating the use of the technique are presented. Peter N. Marinos |
IEEE Trans. Computers | 1 |
| 1969 | Fuzzy Logic and its Application to Switching SystemsabstractFuzzy logic deals with propositions which may be ascribed values between falsehood and truth (0 and 1) subjectively in either a continuous or a discrete fashion. This is in contrast to ordinary logic (two-valued or k-valued logic) in which a given proposition is ascribed values objectively using either deterministic or probabilistic approaches. Peter N. Marinos |
IEEE Trans. Computers | 1 |