We propose a physics-informed learning framework, called Koopman-PINN, to estimate the parameters of the Heston stochastic volatility model with high-frequency price data in financial markets. The method integrates a nonparametric volatility estimation (known as ART-filter in the literature), moment-based parameter initialization, and a neural Koopman operator constrained by the infinitesimal generator of the underlying stochastic differential equation. By incorporating a generator-based loss, the model bridges Koopman theory and neural modeling to handle partially observed coupled stochastic dynamics in a manner consistent with continuous-time evolution. Across diverse parameter combinations reflecting varying market conditions, Koopman-PINN consistently achieves accurate and robust five-parameter recovery, outperforming existing estimators under a minimal set of initialization assumptions.

This paper presents a sub-harmonic injection-locked sub-sampling PLL (SIL-SSPLL) that realizes a peaking-free jitter transfer. The use of an injection-locked oscillator (ILO) in SSPLL allows the PLL open-loop transfer function to achieve a higher phase margin, thereby enhancing the jitter performance. The study also analyzes the effects of injection locking strength on noise rejection for both the reference signal and the VCO showing that optimal jitter performance can be achieved by properly setting the injection strength. A 13.6 to 17.7 GHz SIL-SSPLL prototype fabricated in a 40 nm CMOS technology demonstrates 74 fs RMS integrated jitter at 15.8 GHz while consuming 22.6 mW of power, leading to an excellent figure of merit (FoM) of -249.1 dBc/Hz.

WiFi passive positioning enables precise target tracking without additional devices, offering a cost-effective solution for elder care, security, and smart homes. However, it faces challenges such as distinguishing stationary humans from static objects and limited angular resolution due to existing hardware constraints. In this paper, we present WiVir, a virtual antenna array system based on commodity WiFi device for passive localization of stationary humans. The system addresses the challenges of channel state information (CSI) measurement errors and innovatively applies the concept of virtual antenna array (VAA) in WiFi-MIMO modes. It overcomes the limitation of the number of antennas in commercial WiFi Network Interface Controller (NIC) and significantly reduces the beam width of beamforming. Beamforming is used to obtain the angle of arrival (AOA), and the beam is analyzed in the frequency domain to generate a two-dimensional angular frequency image. Experimental results show that WiVir achieves 98.4% accuracy and strong robustness in indoor environments, providing precise positioning within a certain angle range.

Although quadrature digital transmitters (DTXs) are particularly useful in wideband scenarios, the interaction between I and Q paths would lead to a non-negligible distortion. Unfortunately, traditional DPD models have not performed well in solving this kind of distortion. For example, memory polynomial (MP) model uses signal amplitude as the fundamental term which is not accurate enough to solve this issue, while 2-D lookup table (2D-LUT) model requires a large number of entries which leads to significant hardware resource consumption. In view of this, we propose an area-efficient dual-path piecewise memory-polynomial (DPP-MP) model, which improves model accuracy while reducing hardware resource consumption. To further reduce the area cost, the model is pruned to 8 terms only and 4 of them are reused. To reduce the logic delay, a new squared multiplier is proposed to replace the default one, which reduces delay by 13.51% and power consumption by 2.56%. This model achieves 36.86% and 66.98% area optimization compared to MP and 2D-LUT, respectively. When applied to a 9-bit quadrature DTX with a 40 MHz 256-QAM signal, this model improves the error vector magnitude (EVM) from -16.38 dB to -35.89 dB with a target average power (Pavg) of 21.07 dBm.

A parallel acceleration strategy and hardware implementation scheme for SAR imaging is proposed to accelerate imaging in high bandwidth, large aperture, and high-density scenarios. Based on traditional SAR imaging, this strategy divides the target image into multiple local images, selecting appropriate radar data within a suitable aperture range based on the locations of each local component. Multiple SAR imaging units operate in parallel, and the local images are stitched together in their original locations to achieve accelerated imaging after cropping. This paper designs the hardware for the SAR imaging units, with its core FFT operations designed as a low-cost reusable structure. By reusing and expanding this hardware unit, the acceleration system can be built with relatively low hardware resources and minimal loss in imaging quality, demonstrating significant application potential for THz radar imaging and high-resolution large-aperture security inspections.

Time-domain signals are typically transformed using a 2D-FFT to generate the Range Doppler Map (RDM) in FMCW radar data processing. Subsequently, 2D-CFAR is applied to the RDM for target detection, while Direction of Arrival (DOA) estimation is utilized to obtain the angular information of the target, thus enabling the acquisition of the target’s spatial information. As the demand for accurate target information increases, the volume of data in each RDM frame also increases. This escalation necessitates significant hardware resources and an area to store the RDM in on-chip SRAM or a large bandwidth to accommodate it in off-chip DDRs. Furthermore, DDR controllers require substantial on-chip resources. To address this challenge, we propose a compression algorithm named APFG, which comprises Amplitude-Phase Transformation (APT), Fix-to-Float (Fix2Float), and Exponential Sharing (ESH). Experimental results demonstrate that this algorithm is applicable across various scenarios, CFAR types, and CFAR configurations, achieving high compression ratios while ensuring the accuracy of CFAR and DOA estimates. Specifically, it achieves a compression ratio of less than 14% when Pceis below 1% and a compression ratio of nearly 30% when Pdeis around 2%.

This paper proposes a quad-core, quad-mode millimeter-wave (mmWave) voltage-controlled oscillator (VCO) utilizing electromagnetic hybrid coupling. This design achieves a wide frequency tuning range and low phase noise, fulfilling the needs of integrated sensing and communication (ISAC) systems. The oscillator addresses the challenge of concurrent oscillations in multi-mode switching oscillators by implementing a switched transconductance network. The VCO also employs a controllable tail transistor array to suppress flicker noise up-conversion across a wide bandwidth, effectively reducing the 1/f3corner frequency and enhancing the phase noise performance. The VCO is fabricated in a 55-nm CMOS process occupying a core area of 0.08 mm2. Measurement results show that the VCO achieves a tuning range of 51.9% spanning from 18.7 to 31.8 GHz, and a phase noise of -110.0 dBc/Hz at 1 MHz offset while consuming 8.4 mW of power, leading to a figure of merit (FoM) of 186.2 dBc/Hz and FoMTof 200.5 dBc/Hz at 1 MHz offset.

This paper proposes a frequency-domain model for fast and accurate prediction of frequency modulation (FM) error in frequency-modulated continuous wave (FMCW) radar chirp generators. Obtaining FM error from the output frequency of a phase-locked loop (PLL) requires lengthy simulation times due to the simulator’s limited frequency quantization accuracy, which can result in discrepancies between simulated and actual performance. To address this issue, the feedback signal (DIV) sent to the phase-frequency detector (PFD) is employed in this study to quickly and accurately determine the FM error through spectrum analysis. During frequency sweeps, the feedback signal with a relatively constant frequency receives the modulating signal directly. To validate the effectiveness of the proposed model, a nested PLL-based frequency synthesizer operating from 24-27.52 GHz is designed in a 55-nm CMOS process. Measurement results show good agreement with those obtained from the model, with the difference between the simulated and measured root mean square (RMS) FM error being less than 22 kHz.

Currently, we are entering the wearable internet era. The use of WiFi signals to perceive human activities or changes in vital signs has gradually become a topic that people are enthusiastic about. Principal Component Analysis (PCA), as a universal data dimensionality reduction algorithm, has been widely applied in the field of WiFi sensing. It is utilized to expedite data processing time and enhance real-time detection capabilities. This paper proposes an acceleration algorithm for PCA in the field of WiFi sensing along with its corresponding hardware architecture. The experimental results indicate that the accuracy of this algorithm can reach 0.9965, and the processing time is approximately 10 ms. Based on the TSMC 22nm technology, the Design Complier (DC) results show that the data throughput of this hardware architecture can reach 24 Gbps@800M, with a gate count of 7571, and the power consumption is 1.6321mW.

This paper presents a hybrid transconductance ($g_{m}$) boosting technique exploiting both transformer coupling and cross-coupled PMOS pair to improve the conversion gain (CG) and noise figure (NF) of mm-wave mixers. To demonstrate the effectiveness of the proposed$g_{m}$-boosting technique, a high-gain and low-noise mixer for 5G FR2 frequency band applications is developed in a 40 nm CMOS process. Transformer-based pole splitting and derivative superposition are employed to enhance the mixer bandwidth and improve linearity. The mixer achieves a peak CG of 20.9 dB, a 30% fractional bandwidth ($f_{BW}$), a minimum NF of 7.7 dB, and an input referred 1-dB compression point of −14 dBm, leading to an excellent figure of merit (FOM) of 11.05. The mixer consumes 15.6 mW of power and occupies a die area of 0.31 mm2.

A 32 fs RMS jitter oversampling phase-locked loop (OSPLL) exploiting a high-gain cross-switching phase detector (CSPD) is proposed. The over-sampling PLL increases sam-pling frequency by 4x, reducing the in-band phase noise and overcoming the loop bandwidth limitation due to the reference frequency. Leveraging the increased loop bandwidth, the noise contribution of the voltage-controlled oscillator (VCO) is sig-nificantly suppressed. The high-gain CSPD adopts a common-mode sampling technique with time interleaving switches to ensure that the reference clock is sampled only at the maximum slew rate. The CSPD with a higher gain facilitates reducing the noise contribution from the phase detector (PD) and the transconductance cell. Additionally, an RC poly-phase filter (PPF) is employed to generate quadrature clocks, avoiding the deterioration of the PLL's low offset frequency phase noise. The PLL is implemented in a 40-nm CMOS process. Simulation results show that the PLL achieves a 32 fs RMS jitter integrated from 10 kHz to 100 MHz and a power consumption of 6.5 mW, resulting in an$FoM_{jitter}$of -261 dB. At 3.84 GHz frequency, the in-band phase noise is -136.8 dBc/Hz at 100 kHz offset.

This paper proposes a high-efficiency low-ripple dual-mode switched-capacitor (SC) DC-DC converter for low-power IoT and wearable device applications. A hybrid self-biased current scheme (HSBC) is developed to achieve low output voltage ripple and fast response. Two supply voltage domains of HSBC and clock drive controller circuit are introduced to reduce the power loss of the control circuit. An on-chip ultra-low-power bias circuit is also designed to minimize the power loss of the bias generator. The proposed DC-DC converter is implemented in a 40 nm CMOS process. Post-layout simulation results show that the converter realizes 1.6-1.8 V to 0.4 V conversion. The peak efficiency is up to 88% at$5\ \mu\mathrm{A}$, and the voltage ripple is less than 10 mV over a load range of 10 nA-$10\ \mu\mathrm{A}$. The response time of the converter is less than$15\ \mu\mathrm{s}$.

This paper proposed a cascaded harmonic enhanced injection-locked frequency tripler fabricated in a 40-nm CMOS process. In order to suppress the fundamental signal and the second harmonic signal, an injection-locked doubler is explored, and then the obtained ×2 frequency signal is mixed with the fundamental signal to realize the third harmonic signal and then the third harmonic signal is injected into the tank of the injection-locked frequency selection network to improve the output power. The tripler achieves a fundamental suppression over -69 dBc and a second harmonic suppression over -66 dBc. The output power over the entire locking range from 71.5 to 86.7 GHz is larger than 5.5 dBm. The chip occupies a die area of 0.25 × 0.35mm2and dissipates 20 mW of power.

This paper presents a continuous frequency switching zig-zag voltage-controlled oscillator (VCO) to overcome the frequency discontinuity problem during the band switching process in multi-band wideband VCOs. Complementary PMOS and NMOS varactors are explored to realize opposite VCO tuning gains with high linearity. The VCO reduces the nonlinearity of the transmitted chirp in frequency-modulated continuous-wave (FMCW) radars, improving the range resolution. Implemented in a 40-nm CMOS technology, the proposed zig-zag multi-band VCO shows a simulated maximum peak frequency error of 10 MHz over 23.4-27.6 GHz frequency range, a −106.6 dBc/Hz phase noise at 1 MHz offset, and a −183.1 dBc/Hz FoM while consuming 12.69 mW power.

This paper proposes and experimentally validates a novel WiFi-based radar model for indoor WiFi sensing, which enables accurate measurement of the radial velocity of objects. A human respiratory monitoring system based on the proposed WiFi radar model is developed. The respiratory monitoring system also leverages principal component analysis (PCA) on the MIMO WiFi channel state information ratio (CSIR) information to extract the components related to human activities. Doppler frequency of respiratory motion is obtained from time-frequency analysis of the CSIR through short-time Fourier transform (STFT). Experimental results show that the WiFi-based radar model achieves high accuracy in velocity measurement with an average error of less than 1.5% and can be used to real-time monitor the respiration rate.

This paper presents a wideband millimeter wave (mmW) LNA fabricated in a 55-nm CMOS process. Inter-stage transformer peak splitting and gain equalization techniques are proposed to improve bandwidth and gain flatness. A transformer- based anti-phase coupling (TBAC) method is developed to enhance effective transconductance boosting, while optimizing noise figure (NF). The LNA achieves a peak gain of 11.8 dB with a gain variation of less than ±0.8 dB, a flat gain bandwidth (FGBW) of 15 GHz (66-81 GHz) and a BW-3dB of 20 GHz (64-84 GHz). The measured NFmin is 5.09 dB at 75 GHz and the input-referred 1dB compression point (IPidB) is -5.8 dBm at 78 GHz. The LNA consumes 40 mA from 1 V power supply.

This paper presents a quadrature frequency synthesizer (QFS) utilizing a switched-coupled slotted inductor (SCSI)-based voltage-controlled oscillator (VCO) to simultaneously improve the reference spurs and out-of-band phase noise while achieving a wide frequency tuning range for multiband 5G mm-Wave (mmW) applications. The QFS is implemented in a 55 nm CMOS process, achieving a reference spurs of -64 to -72 dBc, an in-band phase noise of -81.7 to -87 dBc/Hz at 100 kHz offset and an out-of-band phase noise of -119.1 to -125.4 dBc/Hz at 10 MHz offset, respectively, over the entire 19.89 to 26.35 GHz frequency locking range. The RMS jitter for a 19.89 GHz carrier is 118.7 fs, corresponding to a jitter FOM of -238.47 dB. The chip occupies a die area of 1.31 × 2.13 mm2including the testing pads and dissipates 101 mW of power.

This paper presents a Ka-band integer-N quadrature frequency synthesizer for 5G mm-wave communication applications. It utilizes a dual co-tuning in-phase injection-coupled quadrature voltage-controlled oscillator (IPIC-QVCO) including differential coplanar waveguide (DCPW), digitally-controlled coarse co-tuning varactor array (DCCVA), and analog-controlled fine co-tuning varactors (AFCV) and a matched injection-locked frequency divider (ILFD) to achieve wide locking range (LR), low phase noise, and small phase error. Even fabricated in low cost and large parasitic 0.13 μm CMOS, it still achieves 21.9% LR from 26.7 to 33.27 GHz, the phase noise is -114.06 dBc/Hz at 10 MHz offset from 29.832 GHz carrier, the RMS jitter is 198.8 fs, and the reference spurs are less than -51.3 dBc.

Machine translation is increasingly used to support multilingual communication. Because of unavoidable translation errors, multilingual communication cannot accurately transfer information. We propose to shift from the transparent channel metaphor to the human-interpreter (agent) metaphor. Instead of viewing machine translation mediated communication as a transparent channel, the interpreter (agent) encourages the dialog participants to collaborate, as their interactivity will be helpful in reducing the number of translation errors, the noise of the channel. We examine the translation issues raised by multilingual communication, and analyze the impact of interactivity on the elimination of translation errors. We propose an implementation of the agent metaphor, which promotes interactivity between dialog participants and the machine translator. We design the architecture of our agent, analyze the interaction process, describe decision support and autonomous behavior, and provide an example of repair strategy preparation. We conduct an English-Chinese communication task experiment on tangram arrangement. The experiment shows that, compared to the transparent-channel metaphor, our agent metaphor reduced human communication effort by 21.6%.

QoS computation plays an important role in Web service selection. It involves property value preprocessing aspect, user satisfaction calculation aspect, and aggregation of multiple QoS properties aspect. However, little attention has been paid to users participating in QoS computation. In this paper, we examine QoS computation from the angle of experienced users and novice users. An experienced user is able to be more active in providing configuration information such as expected boundary of a QoS property, distribution function of user satisfaction, and the aggregation weight of each QoS property. While a novice user has limited experience to do this. Based on the study of user-centered factors in QoS computation, we propose a user-centered QoS computation, which provides a new choice of normalization in property value preprocessing aspect, an approach of approximation in user satisfaction calculation aspect, and a weight suggestion way in aggregation of multiple properties aspect. A case study in translation service selection shows that the proposed user-centered QoS calculation is more efficient for novice users than random configuration, and much more efficient for experience users.