An accelerated fault simulation approach for path delay faults is presented. The distinct features of the proposed fault simulation method consist in the application of parallel processing of patterns at all stages of the calculation procedure, its versatility to account for both robust and nonrobust decision of path delay faults, and its capability of efficiently maintaining large numbers of path faults to be simulated.>

The authors present an extension of the automatic test pattern generation system SOCRATES to a hierarchical test pattern generation system for combinational and scan-based circuits. The proposed system is based on predefined high-level primitives, e.g., multiplexers and adders. The exploitation of high-level primitives leads to significant improvements in implication, unique sensitization, and multiple backtrace, all of which play a key role in the efficiency of any automatic test pattern generation (ATG) system. In order to perform deterministic ATG and fault simulation for internal faults of high-level primitives, the high-level primitives are dynamically expanded to their gate-level realization. A number of experimental results, achieved on circuits with several tens of thousands of primitives, demonstrate the efficiency of the proposed approach in terms of CPU time, fault coverage, and memory requirements.>

The authors present DYNAMITE, a versatile and efficient automatic test pattern generation system for path delay fault. Based upon a ten-valued and a three-valued logic, the deterministic test pattern generation algorithm incorporated in DYNAMITE is capable of generating both robust and nonrobust tests for path delay faults. Particular emphasis has been placed on coping with the main disadvantage of the path delay fault model. The distinct features of DYNAMITE consist of the application of a powerful implication procedure and a stepwise path sensitization procedure, which has the capability of proving large numbers of path faults as redundant by a single test generation attempt. The delay test generation process is further optimized by the use of a new path selection procedure which aims at the identification of paths, which can successfully be sensitized, and the elimination of redundant, i.e., unsensitizable, paths.>

This paper presents an accelerated fault simulation approach for path delay faults. The distinct features of the proposed fault simulation method consist in the application of parallel processing of patterns at all stages of the calculation procedure, its versatility to account for both robust and non-robust detection of path delay faults, and its capability of efficiently maintaining large numbers of path faults to be simulated.

It is demonstrated that the exploitation of high-level primitives (HLPs) and, in particular, of the knowledge concerning their function in ATPG (automatic test pattern generation) leads to significant improvements in implication, unique sensitization, and multiple backtrace. Motivated by this observation and the necessity of covering all faults inside HLPs, the authors present the extension of the ATPG system SOCRATES to hierarchical test pattern generation, which is based upon HLPs and the strategy of dynamically expanding the HLPs to their gate-level realization, at most one at a time. Experimental results have substantiated that the proposed approach performs significantly better in terms of CPU time, elapsed time, fault coverage, and memory requirements than a gate-level ATPG algorithm. It is expected that the extended SOCRATES algorithm will be capable of coping with circuits consisting of 100000 gates and more within reasonable times, even in a workstation environment.>

The authors present ESSENTIAL, deterministic automatic test pattern generation algorithm for sequential circuits. By combining reverse time processing over time frames and forward processing within time frames, ESSENTIAL avoids the detrimental a priori determination of a topological path to be sensitized or of a primary output, to which the fault effects have to be propagated. Moreover, the proposed test generation approach fully exploits the beneficial techniques that have successfully been used for combinational circuits by the automatic test pattern generation system SOCRATES. In particular, the authors discuss a learning procedure for global implications not only over reconvergent fanout, but also over time frames as well as static and dynamic unique sensitization techniques. After introducing a couple of intelligent heuristics employed for guiding and supporting the decision-making process, the authors report some preliminary but encouraging experimental results.>

The authors present several concepts and techniques aiming at a further improvement and acceleration of the deterministic test-pattern-generation and redundancy identification process. In particular, they describe an improved implication procedure and an improved unique sensitization procedure. While the improved implication procedure takes advantage of the dynamic application of a learning procedure, the improved unique sensitization procedure profits from a dynamic and careful consideration of the existing situation of value assignments in the circuit. As a result of the application of the proposed techniques, SOCRATES is capable of both successfully generating a test pattern for all testable faults in a set of combinational benchmark circuits, and of identifying all redundant faults with less than ten backtrackings.>

An automatic test pattern generation system, SOCRATES, is presented. SOCRATES includes several novel concepts and techniques that significantly improve and accelerate the automatic test pattern generation process for combinational and scan-based circuits. Based on the FAN algorithm, improved implication, sensitization, and multiple backtrace procedures are described. The application of these techniques leads to a considerable reduction of the number of backtrackings and an earlier recognition of conflicts and redundancies. Several experiments using a set of combinational benchmark circuits demonstrate the efficiency of SOCRATES and its cost-effectiveness, even in a workstation environment.>

The principles of fault simulation and fault grading are introduced by a general description of the problem. Based upon the well-known concept of restricting fault simulation to the fanout stems and of combining it with a backward traversal inside the fanout-free regions of the circuit, proposals are presented to further accelerate fault simulation and fault grading. These proposals aim at parallel processing of patterns at all stages of the calculation procedure, at reducing the number of fanout stems for which a fault simulation has to be carried out, and at taking advantage of structural characteristics of the circuit. An experiment with a set of benchmark circuits demonstrates the efficiency of the proposed approaches.