A novel approach, called FACT (fault analysis and critique technique), that can provide facts about untestable and difficult-to-test faults in sequential designs by identifying them in a deterministic way is proposed. The importance of identifying such faults early in the design cycle is discussed, along with their effect on computer execution time, increasing it by as much as 65%, during test generation and simulation. These are demonstrated with real examples. Details of the underlying concepts used in FACT are explained. Some experimental results are presented.>

Bit-sliced microprocessors are representative of an important class of LSI components that can be interconnected in a regular way to construct many useful types of digital systems. This paper develops an analytic test generation methodology for bit-sliced systems. A formal model C for a 1-bit bit-sliced microprocessor is defined which has the main features of many commercially available microprocessors. Using a functional fault model instead of the usual stuck-line fault model, a technique is presented for deriving a complete and near-minimal sequence of tests for C. The basic cell C is extended to form two more general cells Ck and Ck. n. Ck is a k-bit version of C, while Ck, n is Ck with an n × k-bit scratchpad RAM. The internal structure of C4,16 closely resembles that of the AMD 2901 processor slice. Test sequences for these cells are derived in much the same way as for C. It is shown that the test sequence for a single cell (C, Ck, or Ck, n) can easily be extended to a test sequence for an array of N identical cells with no increase in the number of tests required. It is observed that for test generation purposes, bit-sliced microprocessors can be viewed as C-testable iterative logic arrays, which require a constant number of test patterns independent of array size. Some new results on test generation for C-testable systems are presented, as well as a method for modifying iterative logic arrays to make them C-testable.

Bit-sliced systems are formed by interconnecting identical slices or cells to form a one-dimensional iterative logic array (ILA). This paper presents several design techniques for constructing easily testable bit-sliced systems. Properties of ILA's that simplify their testing are examined. C-testable ILA's, which require a constant number of test patterns independent of the array size, are characterized, and a method for making an arbitrary ILA C-testable is presented. A new testability concept for arrays called I-testability is introduced. I-testability ensures that identical test responses can be obtained from every cell in an ILA, and thus simplifies response verification. I-testable ILA's are characterized, as well as CI-testable arrays, which are simultaneously C- and I-testable. A method of making an arbitrary ILA CI-testable is presented. The application of C- and I-testing to the design of bit-sliced (micro-) computers is investigated. For this purpose a family of easily testable processor slices is described. The design of a self-testing CPU based on I-testing is discussed, and compared with a more conventional self-testing design.