Demo Data from VLDB 2026 / reviewers in the wild / expert
Praveen Ghanta
dblp:73/5928
· DBLP profile ↗
7ranked-venue papers
3as first author
0since 2021 · last 2006
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 7 · 3 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Electronic design automation · 78% Performance modeling and evaluation · 11% Integrated circuit design · 11% |
Topics — the 11 heaviest of 11, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
interconnect modeling |
0.1 | 1 | 2006 | Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006 |
Integrated circuit design
low-power circuit design |
0.1 | 1 | 2006 | Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits · DAC 2006 |
Electronic design automation
physical design |
0.1 | 1 | 2006 | Stochastic variational analysis of large power grids considering intra-die correlations · DAC 2006 |
Electronic design automation › physical design
power grid analysis |
0.1 | 1 | 2006 | Stochastic variational analysis of large power grids considering intra-die correlations · DAC 2006 |
Electronic design automation › yield analysis
process variation modeling |
0.1 | 1 | 2006 | Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006 |
Performance modeling and evaluation › statistical analysis
statistical modeling |
0.1 | 1 | 2006 | Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits · DAC 2006 |
Electronic design automation › timing analysis
statistical timing analysis |
0.1 | 1 | 2006 | Stochastic variational analysis of large power grids considering intra-die correlations · DAC 2006 |
Electronic design automation › circuit analysis
variational analysis |
0.1 | 1 | 2006 | Stochastic variational analysis of large power grids considering intra-die correlations · DAC 2006 |
Electronic design automation
design for manufacturability |
0.0 | 1 | 2006 | Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits · DAC 2006 |
Electronic design automation › yield analysis
parametric yield |
0.0 | 1 | 2006 | Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006 |
Electronic design automation
timing analysis |
0.0 | 1 | 2006 | Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006 |
Methods — techniques the papers use, named apart from their topics
monte carlo simulation · 0.1principal component analysis · 0.1orthogonal polynomial expansions · 0.1karhunen-loéve expansion · 0.1karhunen-loève expansion · 0.1hermite polynomial expansion · 0.1galerkin method · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2006 | Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuitsabstractThis paper proposes the use of Karhunen-Loève Expansion (KLE) for accurate and efficient modeling of intra-die correlations in the semiconductor manufacturing process. We demonstrate that the KLE provides a significantly more accurate representation of the underlying stochastic process compared to the traditional approach of dividing the layout into grids and applying Principal Component Analysis (PCA). By comparing the results of leakage analysis using both KLE and the existing approaches, we show that using KLE can provide up to 4-5x reduction in the variability space (number of random variables) while maintaining the same accuracy. We also propose an efficient leakage minimization algorithm that maximizes the leakage yield while satisfying probabilistic constraints on the delay. Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Praveen Ghanta, Yu Cao 0001 |
DAC | 3 |
| 2006 | Stochastic variational analysis of large power grids considering intra-die correlationsabstractFor statistical timing and power analysis that are very importantproblems in the sub-100nm technologies, stochastic analysis of power grids that characterizes the voltage fluctuations due to process variations is inevitable. In this paper, we propose an efficient algorithm for the variational analysis of large power grids in the presence of a significant number of Gaussian intra-die process variables that are correlated. We consider variations in the power grid's electrical parameters as spatial stochastic processes and express them as linear expansions in an orthonormal series of random variables using the Karhunen-Loéve(KLE) method. The voltage response is then represented as an orthonormal polynomial series and the coefficients are obtained optimally using the Galerkin method. We propose a novel method to separate the stochastic analysis for the random variables that effect only the inputs (e.g, drain currents) and for those that effect the system parameters as well (e.g., conductance, capacitance). We show that this parallelism can result in significant speed-ups in addition to the speed-ups inherent to Galerkin-based methods. Our analysis has been applied to several industrial power grids and the results show speed-ups of up to two orders of magnitude over Monte Carlo simulations for comparable accuracy. Praveen Ghanta, Sarma B. K. Vrudhula, Sarvesh Bhardwaj, Rajendran Panda |
DAC | 1 |
| 2006 | A framework for statistical timing analysis using non-linear delay and slew modelsabstractIn this paper we propose a framework for Statistical Static Timing Analysis (SSTA) considering intra-die process variations. Given a cell library, we propose an accurate method to characterize the gate and interconnect delay as well as slew as a function of underlying parameter variations. Using these accurate delay models, we propose a method to perform SSTA based on a quadratic delay and slew model. The method is based on efficient dimensionality reduction technique used for accurate computation of the max of two delay expansions. Our results indicate less than 4% error in the variance of the delay models compared to SPICE Monte Carlo and less than 1% error in the variance of the circuit delay compared to Monte Carlo simulations. Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula |
ICCAD | 2 |
| 2006 | Hermite Polynomial Based Interconnect Analysis in the Presence of Process VariationsabstractVariations in the interconnect geometry of nanoscale ICs translate to variations in their performance. The resulting diminished accuracy in the estimates of performance at the design stage can lead to a significant reduction in the parametric yield. Thus, determining an accurate statistical description (e.g., moments, distribution, etc.) of the interconnect's response is critical for designers. In the presence of significant variations, device or interconnect model parameters such as wire resistance, capacitance, etc., need to modeled as random variables or as spatial random processes. The corner-based analysis is not accurate, and simulations based on sampling require long computation times due to the large number of parameters or random variables. This study proposes an efficient method of computing the stochastic response of interconnects. The technique models the stochastic response in an infinite dimensional Hilbert space in terms of orthogonal polynomial expansions. A finite representation is obtained by projecting the infinite series representation onto a finite dimensional subspace. The advantage of the proposed method is that it provides a functional representation of the response of the system in terms of the random variables that represent the process variations. The proposed algorithm has been implemented in a procedure called orthogonal polynomial expansions for response analysis (OPERA). Results from OPERA simulations on a number of design test cases match well with those from the classical Monte Carlo simulation program with integrated circuits emphasis (SPICE) and from perturbation methods. Additionally, OPERA shows good computational efficiency: speedup of up to two orders of magnitude have been observed over Monte Carlo SPICE simulations. Sarma B. K. Vrudhula, Janet Roveda, Praveen Ghanta |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 3 |
| 2005 | Stochastic Power Grid Analysis Considering Process VariationsabstractIn this paper, we investigate the impact of interconnect and device process variations on voltage fluctuations in power grids. We consider random variations in the power grid's electrical parameters as spatial stochastic processes and propose a new and efficient method to compute the stochastic voltage response of the power grid. Our approach provides an explicit analytical representation of the stochastic voltage response using orthogonal polynomials in a Hilbert space. The approach has been implemented in a prototype software called OPERA (Orthogonal Polynomial Expansions for Response Analysis). Use of OPERA on industrial power grids demonstrated speed-ups of up to two orders of magnitude. The results also show a significant variation of about /spl plusmn/35% in the nominal voltage drops at various nodes of the power grids and demonstrate the need for variation-aware power grid analysis. Praveen Ghanta, Sarma B. K. Vrudhula, Rajendran Panda, Janet Roveda |
DATE | 1 |
| 2004 | Analytical expressions for phase noise eigenfunctions of LC oscillators
Praveen Ghanta, Jaijeet S. Roychowdhury |
ASP-DAC | 1 |
| 2004 | Stochastic analysis of interconnect performance in the presence of process variationsabstractDeformations in interconnect due to process variations can lead to significant performance degradation in deep sub-micron circuits. Timing analyzers attempt to capture the effects of variation on delay with simplified models. The timing verification of RC or RLC networks requires the substitution of such simplified models with spatial stochastic processes that capture the random nature of process variations. The present work proposes a new and viable method to compute the stochastic response of interconnects. The technique models the stochastic response in an infinite dimensional Hilbert space in terms of orthogonal polynomial expansions. A finite representation is obtained by using the Galerkin approach of minimizing the Hilbert space norm of the residual error. The key advance of the proposed method is that it provides a functional representation of the response of the system in terms of the random variables that represent the process variations. The proposed algorithm has been implemented in a procedure called OPERA, results from OPERA simulations on commercial design test cases match well with those from the classical Monte Carlo SPICE simulations and from perturbation methods. Additionally OPERA shows good computational efficiency: speedup factor of 60 has been observed over Monte Carlo SPICE simulations. Janet Roveda, Praveen Ghanta, Sarma B. K. Vrudhula |
ICCAD | 2 |