This paper introduces an analog multi-channel millimeter-wave transceiver architecture that offers advantages in terms of low hardware complexity and computational efficiency compared to digital beamforming and hybrid beamforming techniques. Also, it is known that analog beamforming with a single phase-shifter network faces limitations in maintaining consistent accuracy across a wideband spectrum. To this end, the proposed architecture leverages the inherent bandwidth-splitting property of the multi-channel transceiver. Thus, each sub-band signal is processed by its corresponding channel in the transceiver with an independent analog beamformer per channel. This approach can significantly improve the beamforming accuracy in a wideband communication system such as 5G and future 6G cellular networks. The simulation results demonstrate that increasing the channels in the multi-channel transceiver enables multi-channel analog beamforming to achieve a comparable bit-error-rate (BER) performance to digital beamforming when interference is not considered. Moreover, when interference is present, the proposed multi-channel analog beamforming exhibits enhanced resilience to high power interference compared with digital beamforming with limited analog-to-digital conversion resolution.

This paper investigates multi-channel machine learning (ML) techniques in the presence of receiver nonlinearities and noise, and compares the results with the single-channel receiver architecture. It is known that the multi-channel architecture relaxes the sampling speed requirement of analog to digital conversion and provides significant robustness to clock jitter and front-end noise due to the bandwidth-splitting property inherent in these receivers. However, when a high-voltage swing signal is used in a wireline communication link, the received signal suffers from third-order harmonic distortions and inter-modulation products caused by the nonlinearity profile of the analog front-end (AFE). To this end, this paper proposes the channel decision passing (CDP) algorithm in combination with nonlinear feedback cancellation as a low-complexity candidate for nonlinearity mitigation and compares the performance of this solution with other well-known ML algorithms. Simulation results show significant improvement in a multi-channel receiver architecture equipped with nonlinear feedback cancellation and CDP in comparison with its single-channel counterpart under practical nonlinearity profiles and noise conditions.

This paper demonstrates a low complexity, computationally efficient method for the real-time calibration of Swept Source Optical Coherence Tomography (SS-OCT) systems. In this work, Interpolated Discrete Fourier Transform (IpDFT) based algorithms were explored as a highly efficient alternative for instantaneous frequency measurement and wavenumber calibration of fast optical swept sources. Various IpDFT based methods are implemented and results are evaluated against commonly performed calibration techniques such as Hilbert transformation. Simulation shows execution times decisively improved by up to a factor of ten, depending on observational window length. Axial resolution was also slightly improved. Moreover, the inverse tangent and phase unwrapping steps necessary for Hilbert transform calibration techniques are eliminated, vastly reducing circuit implementation complexity and making the system suitable for future inexpensive, power efficient, on-chip solutions in SS-OCT post-processing.

A process-variation resilient current mode logic (CML) is presented. The proposed CML employs time-reference-based adaptive biasing chain with replica load to address performance degradation over the process variations. It adjusts variable load resistor to simultaneously regulate time constant, voltage swing, level shifting, and DC gain. The prototype demonstrates the process-variation resiliency of the proposed solution by showing performance degradation over the process corners. Over 20% of polygate resistance variation, the proposed CML suppresses the degradation of speed and rms jitter less than 4.3% and 0.15 ps while conventional CML results in 13% and 3.8-ps degradation, respectively.

The traditional Nyquist sampling architecture does not provide a feasible solution in a large multi-channel ultrasound imaging system. The main issues are the huge data volume after the analog-to-digital interface, high power consumption, and circuit complexity at both the front-end and mid-end. This paper presents a Compressed Digital Beamformer (CDB) framework for the design of an ultrasound imaging system with a large transducer array (≥ 1024) operating at a moderate carrier frequency (≥ 5 MHz). Simulations demonstrate that the proposed CDB framework achieves a Compression Ratio (CR) of 0.1 and Mean Square Error (MSE) of -27.7 dB with 4 quantization bits.

Next-generation Wireless Body Sensor Networks (WBSNs) calls for miniaturization and power-efficient integration for long-term monitoring, real-time diagnostics and patient-centered healthcare solutions. However, state-of-the-art WBSN prototypes remain challenged by stringent power constraints and large form factors. The recently proposed asynchronous compressive sensing scheme suggests an efficient way to improve power consumption by reducing the data volume in energy-hungry radio links. In this paper, we present a modified front-end called Asynchronous Binary Compressive Sensing (ABCS) for WBSNs. A low-cost reconstruction method is proposed that exploits the embedded binary signal structure in the ABCS. By incorporating binary amplitude as a prior, better signal recovery performance is obtained comparing with the traditional approaches. Analyses and simulations with an ECG recording confirm the ABCS front-end outperforms the conventional CS approaches in terms of hardware complexity, power consumption and system flexibility.

A digital delay-locked loop (DLL) suitable for generation of multiphase clocks in applications such as time-interleaved and pipelined analog-to-digital converters (ADCs) locks in a very wide (40×) frequency range. The DLL provides 12 uniformly delayed phases, free of false harmonic locking. A two-stage digital split-control loop is implemented: a fast-locking coarse acquisition is achieved in four cycles using binary search; a fine linear loop achieves low jitter (9 ps rms @ 600 MHz) and tracks process, voltage, and temperature (PVT) variations. The false harmonic locking detector, the frequency range and the jitter performance among other design considerations are analyzed in detail. The DLL consumes 20 mW and occupies a 470 μm × 800 μm in 0.13 μm CMOS.

This paper investigates the sensitivity of continuous-time (CT) delta-sigma analog-to-digital converters (ADCs), candidate architectures for multi-standard and software-defined radio receivers, to feedback pulse-width jitter (PWJ) in presence of blocker signals received at the ADC input. A comparison between delta-sigma modulators with feedforward (FF) and feedback (FB) loop filter structures in terms of robustness to digital-to-analog converter (DAC) PWJ, in presence of blockers, is performed. Analysis and discussions developed in the paper are verified by CT simulations in Matlab/Simulink® and simulations results show good agreement with the theoretical expectations. It is shown that the PWJ induced errors due to out-of-band (OOB) blockers in the feedback path dominate the total in-band noise power (IBN) in FF delta-sigma structures and can cause a reduction in the achievable dynamic range that can be as large as 12 dB (2 bits of resolution) in case of using a non-return-to-zero DAC waveform. On the other hand, for same blocker levels at the modulator input, PWJ induced errors caused by OOB blockers have negligible contribution to the IBN in FB structures, owing to their stronger low-pass filtering characteristic and hence higher attenuation of OOB blockers.

We propose a novel parallel mixed-signal compressive spectrum sensing architecture for cognitive radios (CRs) with a detailed study of the signal modeling. The mixed-signal compressive sensing is realized with a parallel segmented compressive sensing (PSCS) architecture, which not only can filter out all the harmonic spurs that leak from the local random generator, but also provides a tradeoff between the sampling rate and the system complexity such that a practical hardware implementation is possible. We consider application of the architecture to do spectrum estimation, which is the first step for spectrum sensing in CRs. The benefit of prior knowledge about the input signal's structure is explored and it is shown that this can be exploited in the PSCS architecture to greatly reduce the sampling rate.

A parallel structure to do spectrum sensing in Cognitive Radio (CR) at sub-Nyquist rate is proposed. The structure is based on Compressed Sensing (CS) that exploits the sparsity of frequency utilization. Specifically, the received analog signal is segmented or time-windowed and CS is applied to each segment independently using an analog implementation of the inner product, then all the samples are processed together to reconstruct the signal. Applying the CS framework to the analog signal directly relaxes the requirements in wideband RF receiver front-ends. Moreover, the parallel structure provides a design flexibility and scalability on the sensing rate and system complexity. This paper also provides a joint reconstruction algorithm that optimally detects the information symbols from the sub-Nyquist analog projection coefficients. Simulations showing the efficiency of the proposed approach are also presented.

We consider a mixed-signal ultra wideband (UWB) direct-sequence spread-spectrum (DS-SS) receiver. The receiver expands the signal over a basis set, and then operates on the basis coefficients. An analog computation of the basis coefficients efficiently parallelizes the signal for digital processing, relaxing the sampling requirements and enabling parallel digital processing at a much lower rate. Bit error rate (BER) performance is evaluated, as well as distortion due to basis truncation. The parallel processing also facilitates efficient interference mitigation. Various models for interference including adjacent multicarrier interference are developed and analyzed. Several simulation results confirm the analysis and provide insight into quantization error, basis truncation distortion, and the impact of the UWB channel. We show that in the AWGN uncoded case for SNR < 10 dB, the receiver can be operated at almost half the Nyquist rate with only 1 dB of performance loss. Moreover, when a common convolutional code is employed, the aggregate sampling rate can be 37.5% lower than Nyquist rate with little loss in receiver performance.

This paper introduces a multicarrier communication receiver for broadband applications based on analog to digital conversion (ADC) of the received signal in the frequency domain. The samples of the spectrum of the received signal are used in the digital receiver to estimate the transmitted symbols through a matched filter operation in the discrete frequency domain. The proposed receiver is aimed at the reception of high information rates in a multicarrier signal with very large bandwidth. Thus, the receiver architecture provides a solution to some of the challenging problems found in the implementation of conventional wideband multicarrier receivers based on time-domain ADC, since It efficiently parallelizes the A/D conversion reducing the sampling speed requirements. We show that the sampling rate requirements are relaxed as the number of frequency samples is increased, which introduces a trade-off between complexity and sampling rate. The new receiver possesses additional advantages, including scalability with increasing frequency samples, the possibility of optimally allocating the available number of bits for the ATD conversion across the frequency domain samples which potentially reduces the distortion introduced by the high-speed ADC, narrowband interference suppression that can be directly carried out in the frequency domain, and inherent robustness to frequency offset which makes it an attractive solution when compared with traditional multicarrier receivers. We also investigate how the proposed receiver responds to common multicarrier communication receiver problems such as phase noise and channel frequency selectivity.

In the UWB multicarrier receiver, after analog to digital conversion (ADC), the samples of the spectrum of the received signal are used in the digital receiver to estimate the transmitted symbols through a matched filter operation in the discrete frequency domain. The proposed receiver is aimed at the reception of high information rates in a multicarrier signal with very large bandwidth. Thus, the receiver architecture provides a solution to some of the challenging problems found in the implementation of conventional wideband multicarrier receivers based on time-domain ADC, since it parallelizes the A/D conversion, reducing the sampling rate. The receiver is also directly applicable to multicarrier ultra-wideband communication receivers. Additional advantages of the proposed receiver include the possibility of optimally allocating the available number of bits for the A/D conversion across the frequency domain samples, narrowband interference suppression that can be directly carried out in the frequency domain, and inherent robustness to frequency offset which makes it an attractive solution when compared with traditional multicarrier receivers.

Ultrawideband systems employ short low-power pulses. Analog receiver designs can accommodate the required bandwidths, but they come at a cost of reduced flexibility. Digital approaches, on the other hand, provide flexibility in receiver signal processing but are limited by analog-to-digital converter (ADC) resolution and power consumption. In this paper, we consider reduced complexity digital receivers, in which the ADC is limited to a single bit per sample. We study three one-bit ADC schemes: 1) fixed reference; 2) stochastic reference; and 3) sigma-delta modulation (SDM). These are compared for two types of receivers based on: 1) matched filtering; and 2) transmitted reference. Bit-error rate (BER) expressions are developed for these systems and compared to full-resolution implementations with negligible quantization error. The analysis includes the impact of quantization noise, filtering, and oversampling. In particular, for an additive white Gaussian noise channel, we show that the SDM scheme with oversampling can achieve the BER performance of a full-resolution digital receiver.

The paper introduces techniques to perform analog-to-digital (A/D) conversion, based on the quantization of the coefficients obtained by the projection of a continuous-time signal over an orthogonal space. This framework for A/D conversion is motivated by the sampling of an input signal in domains which may lead to lower levels of signal distortion and significantly less demanding A/D conversion characteristics. The A/D conversion distortion is reduced by assigning optimal bit rates according to the variance distribution of the coefficients. Moreover, since the quantization of the coefficients is realized at the end of a time window during which the signal is projected, the speed of the quantizers can be much lower than the one needed in conventional time-domain ADCs. In particular, we study ADC in the frequency domain which overcomes some of the difficulties encountered with conventional time-domain A/D conversion of signals with very large bandwidths, such as ultra-wideband (UWB) signals.

Weighted median (WM) filtering structures for complex-valued samples have been proposed but none of them allows the use of complex-valued weights. This paper defines complex-valued weighting for median filters with complex-valued input samples. Two different approaches to the handling of weights in the complex domain are presented, both derived from characteristics of complex-valued linear filters, resulting in two definitions of the complex weighted median filter. The LMS optimizations of the proposed filtering schemes are also presented. Simulations are shown illustrating the performance of the new complex WM filter structures compared with previous approaches to the problem and with classical linear filters.

This paper develops mixed signal equalization solutions for gigabit communications in printed circuit boards (PCBs). The PCB channel, composed by vias and interconnects, distorts and produces signal reflections that deteriorate quality of high speed data transmission. Analog signal processing architectures are necessary to combat the ISI effects introduced by the channel since high speed A/D conversion is a very expensive solution. A novel system description and circuit-level architecture that performs mixed-signal feedforward and feedback equalization in the transmit end is introduced. System level simulations show how this combined FF-FB transmit equalizer outperforms the conventional pre-emphasis structures presented in previous works, with a reasonable compromise in circuit area.