This paper describes a fully automatic standard-cell layoutsynthesis system, CELLERITY. The system is flexible insupporting a wide variety of process technologies and a range oflibrary template styles. The tool is fully automatic and providesseveral options to the user to customize the layout template. Thetool considers performance and yield and generates dense,design-rule correct layouts. Experimental results indicate that thearea of CELLERITY-generated standard cells is competitive withmanually designed cells in a majority of circuits. In block-leveltests of industrial circuits, standard-cell blocks generated usingCELLERITY cells are about equal to the block area produced byusing a manually-designed library. Recently, an embeddedmicrocontroller in a state-of-the-art sub-micron processtechnology was fabricated using CELLERITY-generated standard cells.

We present a novel genetic algorithm-based partitioning scheme for multichip modules (MCM's) which integrates four performance constraints simultaneously: pin count, area, heat dissipation, and timing. We also present a similar partitioning algorithm based on evolutionary programming. Experimental studies demonstrate the superiority of these methods over deterministic Fiduccia-Mattheyes (FM) algorithm and simulated annealing (SA) technique. Our approach performs better than another genetic algorithm-based method recently reported. The adaptive change of crossover and mutation probabilities results in better convergence of the partitioning algorithm.

A model is presented to characterize the relationship between the best solution (incumbent) found by an iterative algorithm (simulated annealing) and the time spent in achieving it. The target application has been chosen to be the placement of cells on a VLSI chip. The model is used to achieve a tradeoff between solution quality and time spent. This gives an idea of the time at which the iterative algorithm should be terminated when the marginal gain in solution quality is smaller than the marginal increase in cost (or time) spent. Nonlinear regression analysis is used to predict the decrease in time with respect to improvement in solution quality. Experimental results on benchmark circuits are presented to show the errors of run-time prediction compared to a static prediction.>