To make three-dimensional (3-D) on-chip interconnect inductance extraction tractable, it is necessary to ignore parasitic couplings without compromising critical properties of the interconnect system. It is demonstrated that simply discarding faraway mutual inductance couplings can lead to an unstable approximate inductance matrix. In this paper, we describe an equipotential shell methodology, which generates a partial inductance matrix that is sparse yet stable and symmetric. We prove the positive definiteness of the resulting approximate inductance matrix when the equipotential shells are properly defined. Importantly, the equipotential shell approach also provably preserves the inductance of loops if they are enclosed entirely within the shells of their segments. Methods for sizing the shells to control the accuracy are presented. To demonstrate the overall efficacy for on-chip extraction, ellipsoid shells, which are a special case of the general equipotential shell approach, are presented and demonstrated for both on-chip and system-level extraction examples.