VLDB 2026 Research / reviewers in the wild / expert
Noëlle Lewis
dblp:73/782 · also Noëlle Milet-Lewis
· DBLP profile ↗
5ranked-venue papers
1as first author
0since 2021 · last 2012
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 1 first-authorArtificial intelligence and machine learning · 1Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 77% Emerging computing paradigms · 23% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
analog and mixed-signal circuits |
0.1 | 1 | 2012 | Application of IP-Based Analog Platforms in the Design of Neuromimetic Integrated Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012 |
Emerging computing paradigms › neuromorphic computing
neuromorphic circuits |
0.0 | 1 | 2012 | Application of IP-Based Analog Platforms in the Design of Neuromimetic Integrated Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012 |
Methods — techniques the papers use, named apart from their topics
platform-based design · 0.1behavioral modeling · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2012 | Application of IP-Based Analog Platforms in the Design of Neuromimetic Integrated CircuitsabstractReuse methodologies are now widely used to design digital circuits. They are based on the concept of intellectual property (IP), or virtual block of computing, characterized by a behavioral model, synthesizable or not. The design reuse for analog integrated systems is much less natural and less standardized. This paper addresses the issue of an analog design flow based on reuse, focusing on three key issues: the formal content of the IP block, the design of a reusable analog IP, and the organization of a design flow centered on an IP library. After a conceptual overview, this paper presents the methodological principles and details examples with a tutorial intention. The objective is to guide the designer involved in the process of developing analog IPs and corresponding design flow. This method is inspired by platform-based design and adapted here on an original case study: the design of full-custom neuromimetic integrated circuits, built from specific analog computational blocks. The development of reusable IPs represents an additional effort, mainly for behavioral modeling and characterization. Nevertheless, the steps illustrated in this case study show that the extra time provides a definite advantage to future design projects. Timothée Levi, Noëlle Lewis, Jean Tomas, Sylvie Renaud |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 2010 | PAX: A mixed hardware/software simulation platform for spiking neural networks
Sylvie Renaud, Jean Tomas, Noëlle Lewis, Yannick Bornat, Adel Daouzli, Michael Rudolph 0002, Alain Destexhe, Sylvain Saïghi |
Neural Networks | 3 |
| 2008 | A real-time setup for multisite signal recording and processing in living neural networksabstractBioelectronic systems using multielectrodes arrays (MEAs) make possible new experiments, based on long term analysis of neural system at the network level. In this paper we present an experimental platform that processes signals from a 60 electrode MEA and runs event (spike, burst, and stimulus artifact) detection and statistic in real-time. The minimum processing task (storage and monitoring) takes 25 mus and the full one takes 60 mus. The data is available for online and offline analysis: on the computer's screen, on the computer's hard disk, and on the TCP/IP layer. Guilherme Bontorin, Colin Lopez, Yannick Bornat, Noëlle Lewis, Sylvie Renaud, Mathieu C. Garenne, Gwendal Le Masson |
ISCAS | 4 |
| 2006 | Automatic procedure generating noise models for discrete-time applicationsabstractThis paper describes an automatic procedure to generate any kind of noise source model, in time domain, including amplitude noise, phase noise or jitter. This approach is particularly suited for discrete-time circuits and systems. The inputs are the noise spectrum characteristics and the output is the VHDL-AMS code of the noise model. As an illustration, examples of a noisy sine wave and a jittered clock are generated, then analysed to validate the procedure. Noëlle Lewis, Guillaume Monnerie, Léo Lewis, Jocelyn Sabatier, Pierre Melchior |
ISCAS | 1 |
| 2003 | Modelling of transient noise sources with VHDL-AMS and normative spectral interpretation
Guillaume Monnerie, Noëlle Lewis, Dominique Dallet, Hervé Levi, M. Robbe |
FDL | 2 |