Large-scale multi-FPGA systems are widely used in modern emulation systems. As a critical part of the multi-FPGA system design flow, TDM signal grouping and package pin assignment directly impact the final placement and routing in the FPGA physical implementation. Poor pin assignments cause severe congestion and timing degradation at the logic-element level, while existing approaches lack accurate congestion modeling during system-level partitioning. This paper presents Chimew, a novel pin assignment methodology that leverages placement prototyping to predict logic-element-level congestion before physical implementation precisely. The proposed method co-optimizes signal grouping and pin placement through iterative refinement guided by congestion-aware cost functions derived from fast global placement. Experimental results demonstrate a 28% congestion reduction and up to 2.87ns less worst negative slack (WNS) compared to industrial tools while achieving a 100% success rate across diverse multi-FPGA benchmarks.

Thoroughly utilizing scale-aware context features to accurately segment entire salient regions remains a significant challenge in salient object detection (SOD) for optical remote sensing images (RSIs). In this letter, we propose a novel dynamic context coordination network (DCC-Net), which is capable of highlighting complete salient regions by exploiting feature coordination across different network levels. DCC-Net is composed of three components: a feature encoder, a bilinear purification (BP) module, and a dynamic context coordination (DCC) module. First, we adopt a standard feature encoder to extract multiscale features. Second, a BP module is proposed to establish a global correlation between horizontal and vertical directions and purify saliency representations. Finally, a DCC module is designed to facilitate context coordination from low to high resolutions by conditioning the convolution kernels dynamic on adjacent context. Comparison experiments are performed on the ORSSD, EORSSD, and ORSI-4199 datasets, demonstrating the superiority of our proposed method against other state-of-the-art methods and verifying the effectiveness of the DCC.

Current methods for salient object detection in optical remote sensing images (RSI-SOD) adhere strictly to the conventional supervised train-test paradigm, where models remain fixed after training and are directly applied to test samples. However, this paradigm faces significant challenges in adapting to test-time images due to the inherent variability in remote sensing scenes. Salient objects exhibit considerable differences in size, type, and topology across RSIs, complicating accurate localization in unseen test images. Moreover, the acquisition of RSIs is highly susceptible to atmospheric conditions, often leading to degraded image quality and a notable domain shift between training and testing phases. In this work, we explore test-time model adaptation for RSI-SOD and introduce a novel multitask collaboration approach to tackle these challenges. Our approach integrates a self-supervised auxiliary task, specifically image reconstruction, with the primary supervised task of saliency prediction to achieve collaborative learning. This is accomplished through an architecture that comprises a shared feature encoder and two distinct task-specific decoders. Most importantly, the self-supervised image reconstruction task optimizes model parameters using unlabeled test-time images, allowing adaptation to test distributions and enabling flexibly scene-dependent representation learning. In addition, we design a cross-task modulation module (CMM) positioned between the task-specific decoders, which fully exploits intertask correlations to enhance the adjustment of saliency representations. Extensive experimental evaluations confirm the superiority of our method across three widely used RSI-SOD benchmarks and validate the robustness of our proposed test-time adaptation strategy against diverse types of RSI corruptions.

Current state-of-the-art methods for salient object detection in optical remote sensing images (RSI-SOD) primarily relies on individual image context to detect salient objects. However, the potential of cross-image contexts remains largely unexplored in existing works, which can provide valuable auxiliary and complementary information for discriminating object representations in RSIs. In this paper, we investigate the utilization of cross-image contextual information for RSI-SOD. We propose a novel memory-based context propagation network (MCP-Net) to harness dataset-level contextual information. MCP-Net incorporates a cross-image dual memory module (CDM) to store dataset-level information and utilize it to generate contextual information for the current image. CDM effectively captures intra-scene variations by leveraging both foreground and background memory banks, resulting in improved object representations. Additionally, we enhance the representations by leveraging scale-aware context information within individual images. To preserve RSI details before memory modules, we introduce a shared attention-guided fusion module (SAF) to align the adjacent network-level features. Extensive evaluation results demonstrate the superior performance of our proposed method compared to state-of-the-art methods on three public benchmarks. These results affirm that the inclusion of cross-image contexts can significantly benefit salient object detection in remote sensing images.

Abstract Falling from a height is the most common accident on construction sites. Vision‐based techniques can be used to automatically monitor the construction sites and give early warnings. In this study, a lightweight object detection method, Efficient‐YOLOv5, was proposed for detecting whether workers are wearing safety harnesses when working at height. Furthermore, a matching‐recheck strategy was proposed to improve the mean average precision (mAP). The safety status evaluation model was designed to evaluate the safety status of workers in different construction scenarios. An edge computing‐based security monitoring and alarm system suitable for deployment on construction sites was proposed to assist manual management. Efficient‐YOLOv5 was trained and evaluated on our newly created dataset. Experiments demonstrated that our proposed method outperformed other comparison methods, as the precision and recall rates were 97.7% and 89.3%, respectively. The mAP was 94%. The rate of frames per second (FPS) was 72, which met real‐time application requirements. Thus, the proposed method could easily be applied in the construction industry.

Although remarkable progress has been made for salient object detection (SOD) in optical remote sensing images (RSIs), the static network design paradigm adopted by existing methods would limit their adaptability to large variations in remote sensing scenes as well as object appearances. In contrast, we explore this research issue from the perspective of generating dynamic network filters in which the parameters are conditioned on specific scene- and location-level contexts. In this paper, we propose a Progressive Context-aware Dynamic Network (PCD-Net) for SOD in RSIs, which adaptively captures context information and adjusts its filtering parameters for saliency detection. PCD-Net adopts an encoder-decoder architecture in which encoded feature representations are progressively decoded by a newly proposed dynamic module, namely Pyramid Scene- and Location-sensitive Dynamic filtering module (PSLD), to generate saliency representations. Furthermore, to transfer effective features from the encoder to the decoder, we construct a Dynamic Transfer Attention (DTA) module to control the interference between the encoder and the decoder in a more flexible way. Extensive evaluations on two commonly-used benchmarks demonstrate the superiority of the proposed method against the existing state-of-the-art methods.

Fully convolutional neural networks (FCNs) have shown outstanding performance in many computer vision tasks including salient object detection. However, there still remains two issues needed to be addressed in deep learning based saliency detection. One is the lack of tremendous amount of annotated data to train a network. The other is the lack of robustness for extracting salient objects in images containing complex scenes. In this paper, we present a new architecture-PDNet, a robust prior-model guided depth-enhanced network for RGB-D salient object detection. In contrast to existing works, in which RGB-D values of image pixels are fed directly to a network, the proposed architecture is composed of a master network for processing RGB values, and a sub-network making full use of depth cues and incorporate depth-based features into the master network. To overcome the limited size of the labeled RGB-D dataset for training, we employ a large conventional RGB dataset to pre-train the master network, which proves to contribute largely to the final accuracy. Extensive evaluations over five benchmark datasets demonstrate that our proposed method performs favorably against the state-of-the-art approaches.

Saliency detection has been an increasingly important tool for ROI selection in image compression. Most previous works on saliency detection are dedicated to conventional images, however, with the rapid development of VR or AR technology, it is becoming more and more important to obtain visual attention for panoramic images. Meanwhile, panoramic images have more potential for improvement in compression performance compared with the conventional case. In this work, we propose an innovative saliency guided ROI selection model. Extensive evaluations show the proposed approach outperforms other methods in saliency accuracy especially for panoramic images. Meanwhile, we improve the compression quality of standard JPEG by using a higher bit rate to encode image regions flagged by our model and lower bit rate elsewhere in the image.

Automatic salient object detection without any supervised labor tends to greatly enhance many computer vision tasks. This paper proposes a novel bottom-up salient object detection framework which considers both foreground and background priors in detecting process. First, a series of foreground seeds are extracted from an image based on surroundedness cue. Then, a foreground-corresponding saliency map is generated via ranking algorithm according to these seeds. In a similar way a series of background seeds are extracted and used for generating a background-corresponding saliency map. Finally, the two saliency maps are fused into one, and subsequently enhanced by geodesic refinement to derive the final saliency map. Extensive experimental evaluation demonstrates the effectiveness of our proposed framework against other outstanding methods.

Saliency detection has received tremendous attention from the research community and has become an increasingly important preprocessing tool in many computer vision tasks, such as object recognition. Saliency detection in the frequency domain possesses great advantages compared with that in the spatial domain due to its computational efficiency and succinct model design. Many excellent frequency domain based models, such as SR, phase spectrum of quaternion Fourier transform, hypercomplex Fourier transform (HFT), have made great progress in predicting human eye fixations. However, there still exists a vital drawback among them-ignoring the different contributions of image channels to saliency detection. In our observation, chrominance component of an image may play an unequally important role as luminance component in different situations. In this letter, we propose a frequency domain based framework, which exploits HFT-based saliency algorithm and finds a way to weigh the importance of different channels in saliency detection across space. In the first step, saliency maps corresponding to different channels are generated independently. In the second step, a combination of both saliency maps is performed using an adaptive entropy-based uncertainty weighting approach. We provide an extensive evaluation and show that our proposed method outperforms nine outstanding eye fixation prediction models on four most commonly-used datasets.

In this paper, an approach to synthesize compressor trees in high-level synthesis is proposed. We target the modern field-programmable gate arrays, which integrate carry chains and support fast ternary adders. Two main improvements are achieved in our approach: 1) based on the proposed modified bitmask analysis, we perform bit-level numerical optimizations to shrink the scale of generated compressor trees and achieve a better area-delay performance; 2) by estimating the arrival time of each multi-input addition operand, we combine the use of generalized parallel counters and ternary adders in compressor trees to further reduce the area while maintaining a similar delay performance. A series of experiments shows that our approach reduces the area significantly while maintaining similar delay performance, as compared to the existing approaches.

In this paper, an approach to synthesize compressor trees in High-level Synthesis (HLS) for FPGAs is proposed. Our approach utilizes the bit-level information to improve the compressor tree synthesis. To obtain the bit-level information targeting compressor tree synthesis, a modified bitmask analysis technique based on prior work is proposed. A series of experimental results show that, compared to the existing heuristic, the average reductions of area and delay are 22.96% and 7.05%. The reductions increase to 29.97% and 9.07% respectively, when the carry chains in FPGAs are utilized to implement the compressor trees.

Applications running concurrently in CMP systems interfere with each other at DRAM memory, leading to poor system performance and fairness. Memory access scheduling reorders memory requests to improve system throughput and fairness. However, it cannot resolve the interference issue effectively. To reduce interference, memory partitioning divides memory resource among threads. Memory channel partitioning maps the data of threads that are likely to severely interfere with each other to different channels. However, it allocates memory resource unfairly and physically exacerbates memory contention of intensive threads, thus ultimately resulting in the increased slowdown of these threads and high system unfairness. Bank partitioning divides memory banks among cores and eliminates interference. However, previous equal bank partitioning restricts the number of banks available to individual thread and reduces bank level parallelism. In this paper, we first propose a Dynamic Bank Partitioning (DBP), which partitions memory banks according to threads' requirements for bank amounts. DBP compensates for the reduced bank level parallelism caused by equal bank partitioning. The key principle is to profile threads' memory characteristics at run-time and estimate their demands for bank amount, then use the estimation to direct our bank partitioning. Second, we observe that bank partitioning and memory scheduling are orthogonal in the sense; both methods can be illuminated when they are applied together. Therefore, we present a comprehensive approach which integrates Dynamic Bank Partitioning and Thread Cluster Memory scheduling (DBP-TCM, TCM is one of the best memory scheduling) to further improve system performance. Experimental results show that the proposed DBP improves system performance by 4.3% and improves system fairness by 16% over equal bank partitioning. Compared to TCM, DBP-TCM improves system throughput by 6.2% and fairness by 16.7%. When compared with MCP, DBP-TCM provides 5.3% better system throughput and 37% better system fairness. We conclude that our methods are effective in improving both system throughput and fairness.

Homotopic routing asks for a path going around holes according to a given “threading”. Paths of different homo-topy types can be used to improve load balancing and routing resilience. We propose the first lightweight homotopic routing scheme that generates constant bounded stretch compared to the shortest path of the same homotopy type. Our main insight is that in a sequence of triangles to traverse, a message always routed to the nearest point on the next triangle in the sequence travels at most a constant times the length of any shortest path going through the same sequence of triangles. Our routing scheme operates on two levels enabled by a coarse triangulation. The top level is used to specify and represent the requested homotopy type, while the bottom level executes the local greedy routing on a triangle sequence. After a preprocessing step that triangulates the given region and creates a minimum-size auxiliary structure, routing operates greedily at two different resolutions. We also present simulation analysis in a variety of settings and show that the paths indeed have small stretch in practice, considerably shorter than the bounds guaranteed by the theory.

DRAM performance and power efficiency considerations are becoming increasingly important. Bank partitioning partitions memory banks among cores and eliminates inter-thread interference, thus improving system performance of shared memory CMP systems. However, it doesn't take into account DRAM power consumption. We propose an application-aware page policy, which exploits potential benefits of page policy to optimize DRAM performance or minimize power consumption. The key idea is to dynamically assign page policy to applications according to their memory characteristics. As an improvement, we propose a power-aware bank partitioning to balance DRAM performance and power consumption. Experimental results show that our proposal increases system performance and significantly improves DRAM power efficiency.

For the increasing market of smart phones, mobile internet devices, and ultra-mobile PCs, mainstream vendors propose two approaches: one is based on ARM SoC, and the other is based on power-efficient x86 processor. However, either approach has its own limitation. The ARM-based approach lacks application software while the x86-based approach does not support flexible SoC extension. To overcome the limitations, we propose the PKUnity86 SoC architecture, which is based on AMBA bus architecture to support fast IP integration. Furthermore, it contains a reduced AMD Geode GX2 processor and several specific designs to support Microsoft Windows and exploit the massive PC software resources.