The first 1.1V-programmable metal-fuse technology in 28nm CMOS technology is reported in this work. The prototyped 1Kb-memory array featuring a$12.4\mu $m2 1T1R bit cell adopts the proposed current-mode programming (CMP) scheme. The CMP scheme achieves a record low programming voltage of 1.1V, surpassing the programming voltages (≥1.6V) required by prior metal-fuse CMOS and FinFET technologies. To ensure successful programming, a closed-loop detector (CLD) employing an on-chip hysteresis comparator detects resistance transition in bit cells during programming. Preliminary experiments demonstrate that the proposed CMP scheme along with CLD achieves a 100% of yield after programming 960 bits at room temperature. Under various programming conditions, the combination of CMP and CLD demonstrates programming robustness, with resistance ratios before and after programming equal to and greater than three orders of magnitude. The measured results suggest a promising method for mitigating over-stress issues associated with high programming voltages used in prior art.

The high-volume manufacturing test ensures the production of defect-free devices, which is of utmost importance when dealing with safety-critical systems. Such a high-quality test requires a deliberately designed scan network to provide a time and cost-effective access to many on-chip components, as included in state-of-the-art chip designs. The IEEE 1687 Std. (IJTAG) has been introduced to tackle this challenge by adding programmable components that enables the design of reconfigurable scan networks. Although these networks reduce the test time by shortening the scan chains’ lengths, the reconfiguration process itself incurs an additional time overhead. This paper proposes a heuristic method for designing customized multi-power domain reconfigurable scan networks with a minimized overall reconfiguration time. More precisely, the proposed method exploits a-priori given non-functional properties of the system, such as the power characteristics and the instruments’ access requirements. For the first time, these non-functional properties are considered to synthesize a well-adjusted and highly efficient multi-power domain network. The experimental results show a considerable improvement over the reported benchmark networks.

Reconfigurable Scan Networks (RSNs) access embedded instruments throughout the whole system lifecycle. To support dependability management by means of RSNs, RSNs themselves must be continuously tested. The paper-at-hand presents the first online periodic test method for RSNs. The developed algorithm generates a short sequence of test patterns, which tests all parts of an RSN. The generated sequence is uploaded on-chip and is applied periodically to avoid fault accumulation in RSNs. The overall test application time is minimized to comply with the timing requirements of the well-known safety standards. The experimental results show that the method is efficient for all considered RSN designs and is scalable with the increasing size and complexity of RSNs.

Reconfigurable Scan Networks (RSNs) access the evaluation results from embedded instruments and control their operation throughout the device lifetime. At the same time, a single fault in an RSN may dramatically reduce the accessibility of the instruments. During post-silicon validation, it may prevent extracting the complete data from a device. During online operation, the inaccessibility of runtime-critical instruments via a defect RSN may eventually result in a system failure. This paper addresses both scenarios above by presenting robust RSNs. We show that by making a small number of carefully selected spots in RSN s more robust, the entire access mechanism becomes significantly more reliable. A flexible cost function assesses the importance of specific control primitives for the overall accessibility of the instruments. Following the cost function, a minimized number of spots is hardened against permanent faults. All the critical instruments as well as most of the remaining instruments are accessible through the resulting RSNs even in the presence of defects. In contrast to state-of-the-art fault-tolerant RSNs, the presented scheme does not change the RSN topology and needs less hardware overhead. Selective hard-ening is formulated as a multi-objective optimization problem and solved by using an evolutionary algorithm. The experimental results validate the efficiency and the scalability of the approach.

Abstract Reconfigurable Scan Networks (RSNs) are widely used for accessing instruments offline during debug, test and validation, as well as for performing system-level-test and online system health monitoring. The correct operation of RSNs is essential, and RSNs have to be thoroughly tested. However, due to their inherently sequential structure and complex control dependencies, large parts of RSNs have limited observability and controllability. As a result, certain faults at the interfaces to the instruments, control primitives and scan segments remain undetected by existing test methods. In the paper at hand, Design-for-test (DfT) schemes are developed to overcome the testability problems e.g. by resynthesizing the initial design. A DfT scheme for RSNs is presented, which allows detecting all single stuck-at-faults in RSNs by using existing test generation techniques. The developed scheme analyzes and ensures the testability of all parts of RSNs, which include scan segments, control primitives, and interfaces to the instruments. Therefore, the developed scheme is referred to as a complete DfT scheme. It allows for a test integration to cover multiple fault locations can with a single efficient test sequence and to reduce overall test cost.

Reconfigurable scan networks (RSNs) enable an efficient reliability management throughout the device lifetime. They can be used for controlling integrated instruments, such as aging monitors or built-in self-test (BIST) registers, as well as for collecting the evaluation results from them. At the same time, they may impose a security threat, since the additional connectivities introduced by the RSN can possibly be misused as a side channel. This article presents an approach for security compliance analysis and resynthesis (SCAR) of RSNs to integrate an RSN compliant with the security properties of the initial design. First, the reachability properties of the original design are accurately computed. The connectivities inside the RSN, which exceed the allowed connectivity of the initial design, are identified using the presented security compliance analysis. Next, all violations are resolved by automated Resynthesis with a minimized number of structural changes. As a result of SCAR, any information leakage due to the RSN integration is prevented, while the accessibility of the instruments through the RSN is preserved. The approach is able to analyze complex control dependencies and obtains a compliant RSN even for the largest available benchmarks.

Self-aware and safety-critical hardware/software systems rely on a variety of embedded instruments, sensors, monitors and design-for-test circuitry to check the system integrity. The access to these internal instruments is supported by standards commonly called iJTAG and employs so called reconfigurable scan networks (RSNs), which are more and more used at runtime, too. They collect periodically and also concurrently the information on the circuit's health state and deliver it to some dependability management unit. The integrity of RSNs is essential for the dependability of self-aware systems and can be ensured by a combination of periodic and concurrent test methods of the RSN itself. The paper at hand presents the first concurrent online test method for RSNs by adding a brief integrity test to each access operation. The presented scheme includes a hardware extension of negligible size, supports offline test, diagnosis and post-silicon validation as well, and is further referred as ROSTI: RSN Online/Offline Self-Test Infrastructure. It exploits the original RSN control signals and does not require any modification of the underlying RSN. The hardware costs are independent of the size of the RSN, and ROSTI is flexible for generating different test sequences for different types of faults. The experimental results validate these characteristics and show that ROSTI is highly scalable.

Reconfigurable Scan Networks (RSNs) have to be tested before they can be used for post-silicon validation, diagnosis or online reliability management. Even a single stuck-at fault in the switch logic of an RSN can corrupt the scan paths and make instruments inaccessible. Testing the switch logic of an RSN is a complex sequential test problem. The existing test schemes for RSNs rely on the assumption that a fault in the switch logic will be detected by the altered length of the erroneously activated scan path. However, often this assumption does not hold and faults in the switch logic remain undetected.In this paper, an automated testability-enhancing resynthesis is presented. First, the testability of the initial RSN is accurately analyzed. If any single fault in the switch logic is undetectable by the altered path length, a small number of scan cells is inserted into the RSN. The presented scheme is applicable to arbitrary RSN designs and is compliant with state-of-the-art test methods and the applicable standards. The experimental results show the efficacy, the efficiency and the scalability of the approach.

Fundamental frequency determination is critical for music and radar signal analysis. In practice, the fundamental frequency is hard to be determined precisely especially when the signal-to-noise ratio (SNR) is low. In this paper, we propose an algorithm using both feature extraction and machine learning to determine fundamental frequency precisely. First, several features, including the correlation in the time-frequency domain and the differences to the previous/next local minima, are extracted. Then, a learning-based classifier is applied. The proposed algorithm can estimate the fundamental frequency accurately even when the SNR is about -9dB and the signal length is only 4 seconds.

Reliable operation, test, debug and diagnosis of complex integrated systems are ensured by embedded instruments, such as sensors, aging monitors or Built-In Self-Test (BIST) registers. Reconfigurable Scan Networks (RSNs) offer a flexible and efficient way to access such test instruments throughout the whole life-cycle. However, improper RSN integration might introduce additional connectivity properties to the device under test (DUT), which can be exploited to perform unauthorized access or cause information leakage. The existence of such additional connectivity through the RSN can compromise the security of the DUT and is considered as a security threat.In this paper, a method is presented to resolve all such security compliance violations. The problem is formulated in terms of Integer Linear Programming (ILP) as a minimum cut problem in multicommodity flow. An efficient heuristic is presented, which, to our knowledge, for the first time allows to consider the whole set of violations simultaneously and thereby to find a minimized number of changes to the RSN structure in order to make it compliant with the initial security requirements of the DUT and prevent the information leakage through the scan chain.

This article describes a diagnosis-aware hybrid concurrent error detection ( DAH-CED ) scheme that can facilitate both off-line and on-line test applications. By using the proposed scheme, not only the probability of detecting errors (on-line) but also the diagnosability of the target circuit (off-line) can be significantly enhanced. The proposed scheme combines the implication-based method with the parity check method. In particular, novel algorithms are developed to identify specific implications for enhancing the diagnosability for the modeled faults proactively. Furthermore, a reduction algorithm is also presented to minimize the number of the employed implications, while no loss on probability of detecting errors and diagnosability is also guaranteed. To the best of our knowledge, this issue is not addressed in the literature. To validate the proposed scheme, not only stuck-at faults but also transition faults are considered to simulate the timing-related errors. The experimental results on nine ITC’99 benchmark circuits show that the diagnosability for stuck-at (transition) faults is enhanced by 6.88% (7.78%) by applying the proposed scheme. As for the probability of detecting errors, 97.73% (97.10%) is achieved for errors caused by stuck-at (transition) faults. Moreover, only 3.11% of implications are needed.

Implication-based concurrent error detection (CED) has been shown to have promising performance for on-line testing. However, many error indication signals may be required for this CED method, and thus incur much additional interconnection. This would result in not only complicated error checking circuits, but also a large compactor design to process the error indication signals. Both would incur high area overhead. In this paper, we present a collapsing technique that can significantly reduce the total number of required error indication signals for implications. This issue has never been addressed in the literature. We find that equivalence and dominance relationships exist between error indication signals, which are quite helpful for signal reduction. Therefore we develop an efficient algorithm to first identify these relationships, and then make good use of them to merge error indication signals without sacrificing the probability of detecting errors. We also employ 19 ISCAS'85 and ITC'99 benchmark circuits to evaluate the effectiveness of the proposed technique. The results show that 48.48% of error indication signals are reduced by our technique on average. This also leads to 39.23% and 34.52% averaged area overhead reduction to the error checking circuit and the compactor design, respectively.

In recent years, a new concurrent error detection method by using invariant relationships inside a circuit, called implications, has been proposed. Algorithms have also been developed to reduce the total number of required implications so as to minimize the incurred area overhead due to implication checking logic. This implication reduction process, however, would result in degradation on the probability of error detection (Pdetection) of the method. In this paper, we analyze the impact of this issue mathematically together with illustration by a real case study. Our analytical results show that just one percent degradation on Pdetectionwould result in millions more errors being undetected per second and thereby significant loss on reliability of the target circuit. To address this issue, we develop a new implication reduction algorithm that guarantees no loss on Pdetection. In our algorithm, the detectability of errors for each candidate implication is carefully evaluated. The evaluation results are then utilized to select the most efficient candidates for detecting all the detectable errors. We also analyze the computation and memory complexity of the proposed algorithm. The experimental results on 28 representative benchmark circuits from ISCAS'85, ISCAS'89, and ITC'99 show that the implication reduction rate of our method (92.59%) is close to that of the previous work (95.8%). Only a small number of additional implications need to be selected to guarantee no loss on Pdetection.

The use of the badminton stroke strategy in the evenly matched game is often the key to victory. In this work, a smart racket based on wearable sensors is proposed to collect the data of swing of badminton. A cell phone APP with machine learning techniques is implemented to record stroke types automatically. In each stroke hit event, this prototype system uses Bluetooth earphone to collect the sound for detecting the accuracy time. It uses the data of IMU in each stroke for determining stroke type. Compared to EMU only solution, the system will reduce the false count of stroke hit. Using cloud techniques could record the training and game record in a long period. Overall the accuracy of stroke hit event is almost 100% by using voice print. The data of EMU is classified by Random Forest or SMO. The accuracy for personal model is 95.91%, and it is 7932% for general model. We develop a stroke record system which is combined with Wearable sensor, Mobile platform and Cloud service.

In this work we propose a hybrid concurrent error detection (CED) scheme that combines the implication-based method with the parity check method. The parity check method is easy to implement and has high probability of detecting errors, while the implication-based method has high flexibility to be easily integrated with other CED methods for improidng the probability of detecting errors. In addition, fault diagnosis capability can even be enabled by integrating implications. We show that by combining these two methods, not only the probability of detecting errors can be significantly increased, but also the diagnosability of the target circuit can be effectively enhanced. A systematical flow is developed to add the required checking logic of implications into the most appropriate locations in the target circuit for detecting undetected errors by the parity check method. This minimizes the total number of the employed implications and thus the incurred area overhead. The experimental results show that 89.08% of area overhead is required yet the probability of detecting errors is improved from 88.32% to 97.73% by the proposed hybrid scheme. The results also show that the achievable diagnosability of our scheme enhances from 91.79% to 96.36% on average. More than 200 equivalent faults also become distinguishable in our scheme.

Performance degradation tolerance (PDT) has been shown to be able to effectively improve the yield, reliability, and lifetime of an electronic product. The focus of PDT is on the particular performance degrading faults (pdef) that only incur some performance degradation of a system without inducing any computation errors. The basic idea is that as long as the defective chips containing only the pdef can provide acceptable performance for some applications, they may still be marketable. Critical issues of PDT to be addressed include the portion of the pdef in a faulty chip and their induced performance degradation. For a typical cache design, most of the possible faults are not pdef. In this brief, we propose a cache redesign method, called PDT cache, where all functional faults in the data-storage cells of a cache (major part of the cache) can be transformed into pdef. By transforming this large number of faults into pdef, a faulty cache becomes much more likely to be still marketable. The proposed design exploits the existing hardware resources and the inherent error resilience scheme to reduce the incurred hardware overhead. The logic synthesis results show that the incurred hardware overhead is only 6.29% for a 32-kB cache. We also evaluate the induced performance degradation under various fault densities using the CPU2000 and CPU2006 benchmark programs. The results show that for a 32-kB cache design, when the fault density is <;1%, only 0.31% performance degradation is incurred. In addition, the scalability of the PDT cache is also evaluated. The results show that a smaller hardware overhead is required for a larger cache, and the performance degradation is independent of the cache associativity and can even be smaller for a larger cache under a given fault density.