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Yasunori Sameshima

dblp:74/1264 · DBLP profile ↗
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3ranked-venue papers
2as first author
0since 2021 · last 2006
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
fault simulation		 0.011994
Multiple signature analysis method using fault simulation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Electronic design automation
hardware verification and test		 0.011994
Multiple signature analysis method using fault simulation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Electronic design automation › hardware verification and test › test response compaction
signature analysis		 0.011994
Multiple signature analysis method using fault simulation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994

Methods — techniques the papers use, named apart from their topics

fault stay map · 0.0aliasing rate minimization · 0.0
YearPublicationVenuePosition
2006 G-lambda: Coordination of a Grid scheduler and lambda path service over GMPLS
Atsuko Takefusa, Michiaki Hayashi, Naohide Nagatsu, Hidemoto Nakada, Tomohiro Kudoh, Takahiro Miyamoto, Tomohiro Otani, Hideaki Tanaka, Masatoshi Suzuki, Yasunori Sameshima
 Future Gener. Comput. Syst.10
1998 A DFT Methodology for High-Speed MCM Based on Boundary-Scan Techniques
Yasunori Sameshima, Tomoo Fukazawa
 Asian Test Symposium1
1994 Multiple signature analysis method using fault simulation
abstract
This paper presents a signature analysis method that achieves a minimum aliasing rate. A fault stay map derived from exact fault simulation without fault dropping indicates whether a fault remains in an output data compressor at each time step. The fault stay map is used to determine the timing of multiple signature observations to achieve the minimum aliasing rate under certain constraints. Experimental results for some combinational circuits modeled on a single stuck-at fault are presented. They show that only two signature observations are required to achieve 0% aliasing in almost all circuits.>
Yasunori Sameshima, Yoshihiro Kitamura, Tomoo Fukazawa
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1