Demo Data from VLDB 2026 / reviewers in the wild / expert
José G. Castaños
dblp:74/2394
· DBLP profile ↗
20ranked-venue papers
3as first author
0since 2021 · last 2014
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 18 · 2 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
5 papers |
Runtime systems and virtual machines · 65% Compilers and program optimization · 16% Programming languages and type systems · 14% | |
| Computer architecture, parallel and distributed computing, and storage systems
8 papers |
High-performance computing · 29% Parallel and multicore computing · 26% Memory systems · 14% |
Topics — the 26 heaviest of 30, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Runtime systems and virtual machines › dynamic compilation
just-in-time compilation |
0.3 | 2 | 2013 | JIT technology with C/C++: Feedback-directed dynamic recompilation for statically compiled languages · ACM Trans. Archit. Code Optim. 2013 On the benefits and pitfalls of extending a statically typed language JIT compiler for dynamic scripting languages · OOPSLA 2012 |
Runtime systems and virtual machines
interpreter design |
0.2 | 1 | 2014 | Eliminating global interpreter locks in ruby through hardware transactional memory · PPoPP 2014 |
Compilers and program optimization
dynamic optimization |
0.2 | 1 | 2013 | JIT technology with C/C++: Feedback-directed dynamic recompilation for statically compiled languages · ACM Trans. Archit. Code Optim. 2013 |
Runtime systems and virtual machines › dynamic compilation
dynamic language compilation |
0.1 | 1 | 2012 | On the benefits and pitfalls of extending a statically typed language JIT compiler for dynamic scripting languages · OOPSLA 2012 |
Parallel and multicore computing › parallel programming models › distributed memory programming models
partitioned global address space |
0.1 | 1 | 2009 | Efficient, portable implementation of asynchronous multi-place programs · PPoPP 2009 |
Operating systems › kernel
lightweight kernel |
0.1 | 1 | 2006 | Blue Gene system software - Designing a highly-scalable operating system: the Blue Gene/L story · SC 2006 |
Memory systems › memory bandwidth
memory bandwidth optimization |
0.1 | 1 | 2006 | Blue Gene system software - Design and implementation of a one-sided communication interface for the IBM eServer Blue Gene® supercomputer · SC 2006 |
Parallel and multicore computing › parallel computing › parallel communication
one-sided communication |
0.1 | 1 | 2006 | Blue Gene system software - Design and implementation of a one-sided communication interface for the IBM eServer Blue Gene® supercomputer · SC 2006 |
High-performance computing
parallel i/o |
0.1 | 1 | 2006 | High performance file I/O for the Blue Gene/L supercomputer · HPCA 2006 |
Distributed systems › distributed communication
remote memory access |
0.1 | 1 | 2006 | Blue Gene system software - Design and implementation of a one-sided communication interface for the IBM eServer Blue Gene® supercomputer · SC 2006 |
Interconnection networks and networks-on-chip › network topology
torus network |
0.1 | 1 | 2006 | Blue Gene system software - Design and implementation of a one-sided communication interface for the IBM eServer Blue Gene® supercomputer · SC 2006 |
Parallel and multicore computing › transactional memory
hardware transactional memory |
0.1 | 1 | 2014 | Eliminating global interpreter locks in ruby through hardware transactional memory · PPoPP 2014 |
High-performance computing › supercomputing
bluegene/l |
0.1 | 2 | 2006 | An overview of the BlueGene/L Supercomputer · SC 2002 High performance file I/O for the Blue Gene/L supercomputer · HPCA 2006 |
High-performance computing
supercomputing |
0.1 | 2 | 2006 | An overview of the BlueGene/L Supercomputer · SC 2002 High performance file I/O for the Blue Gene/L supercomputer · HPCA 2006 |
Runtime systems and virtual machines › dynamic language implementation
dynamic language runtime |
0.0 | 1 | 2012 | On the benefits and pitfalls of extending a statically typed language JIT compiler for dynamic scripting languages · OOPSLA 2012 |
Memory systems › cache
cache organization |
0.0 | 1 | 2002 | Evaluation of a Multithreaded Architecture for Cellular Computing · HPCA 2002 |
Emerging computing paradigms › unconventional computing
cellular computing |
0.0 | 1 | 2002 | Evaluation of a Multithreaded Architecture for Cellular Computing · HPCA 2002 |
Memory systems
memory hierarchy |
0.0 | 1 | 2002 | Evaluation of a Multithreaded Architecture for Cellular Computing · HPCA 2002 |
Processor architecture and microarchitecture
multithreading |
0.0 | 1 | 2002 | Evaluation of a Multithreaded Architecture for Cellular Computing · HPCA 2002 |
Processor architecture and microarchitecture › multiprocessor architecture
synchronization hardware |
0.0 | 1 | 2002 | Evaluation of a Multithreaded Architecture for Cellular Computing · HPCA 2002 |
Integrated circuit design
system-on-chip |
0.0 | 1 | 2002 | An overview of the BlueGene/L Supercomputer · SC 2002 |
High-performance computing › scientific computing systems
adaptive mesh refinement |
0.0 | 1 | 1999 | PARED: A Framework for the Adaptive Solution of PDEs · HPDC 1999 |
Parallel and multicore computing
load balancing |
0.0 | 1 | 1999 | PARED: A Framework for the Adaptive Solution of PDEs · HPDC 1999 |
Storage systems › file systems › distributed file system
parallel file system |
0.0 | 1 | 2006 | High performance file I/O for the Blue Gene/L supercomputer · HPCA 2006 |
Parallel and multicore computing
parallel architecture |
0.0 | 1 | 2002 | Evaluation of a Multithreaded Architecture for Cellular Computing · HPCA 2002 |
Computational science and engineering
partial differential equations |
0.0 | 1 | 1999 | PARED: A Framework for the Adaptive Solution of PDEs · HPDC 1999 |
Methods — techniques the papers use, named apart from their topics
hardware transactional memory · 0.4PGAS · 0.2online profiling · 0.2intermediate representation · 0.2specialization · 0.1profiling · 0.1linux port · 0.1compute node kernel · 0.1interrupt-driven communication · 0.1hierarchical partitioning · 0.1global arrays · 0.1MPI-IO · 0.1ARMCI · 0.1benchmarking · 0.0object-oriented design · 0.0mesh migration · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2014 | Eliminating global interpreter locks in ruby through hardware transactional memoryabstractMany scripting languages use a Global Interpreter Lock (GIL) to simplify the internal designs of their interpreters, but this kind of lock severely lowers the multi-thread per-formance on multi-core machines. This paper presents our first results eliminating the GIL in Ruby using Hardware Transactional Memory (HTM) in the IBM zEnterprise EC12 and Intel 4th Generation Core processors. Though prior prototypes replaced a GIL with HTM, we tested real-istic programs, the Ruby NAS Parallel Benchmarks (NPB), the WEBrick HTTP server, and Ruby on Rails. We devised a new technique to dynamically adjust the transaction lengths on a per-bytecode basis, so that we can optimize the likelihood of transaction aborts against the relative overhead of the instructions to begin and end the transactions. Our results show that HTM achieved 1.9- to 4.4-fold speedups in the NPB programs over the GIL with 12 threads, and 1.6- and 1.2-fold speedups in WEBrick and Ruby on Rails, respectively. The dynamic transaction-length adjustment chose the best transaction lengths for any number of threads and applications with sufficiently long running times. Rei Odaira, José G. Castaños, Hisanobu Tomari |
PPoPP | 2 |
| 2013 | JIT technology with C/C++: Feedback-directed dynamic recompilation for statically compiled languagesabstractThe growing gap between the advanced capabilities of static compilers as reflected in benchmarking results and the actual performance that users experience in real-life scenarios makes client-side dynamic optimization technologies imperative to the domain of static languages. Dynamic optimization of software distributed in the form of a platform-agnostic Intermediate-Representation (IR) has been very successful in the domain of managed languages, greatly improving upon interpreted code, especially when online profiling is used. However, can such feedback-directed IR-based dynamic code generation be viable in the domain of statically compiled, rather than interpreted, languages? We show that fat binaries, which combine the IR together with the statically compiled executable, can provide a practical solution for software vendors, allowing their software to be dynamically optimized without the limitation of binary-level approaches, which lack the high-level IR of the program, and without the warm-up costs associated with the IR-only software distribution approach. We describe and evaluate the fat-binary-based runtime compilation approach using SPECint2006, demonstrating that the overheads it incurs are low enough to be successfully surmounted by dynamic optimization. Building on Java JIT technologies, our results already improve upon common real-world usage scenarios, including very small workloads. Dorit Nuzman, Revital Eres, Sergei Dyshel, Marcel Zalmanovici, José G. Castaños |
ACM Trans. Archit. Code Optim. | 5 |
| 2012 | On the benefits and pitfalls of extending a statically typed language JIT compiler for dynamic scripting languagesabstractWhenever the need to compile a new dynamically typed language arises, an appealing option is to repurpose an existing statically typed language Just-In-Time (JIT) compiler (repurposed JIT compiler). Existing repurposed JIT compilers (RJIT compilers), however, have not yet delivered the hoped-for performance boosts. The performance of JVM languages, for instance, often lags behind standard interpreter implementations. Even more customized solutions that extend the internals of a JIT compiler for the target language compete poorly with those designed specifically for dynamically typed languages. Our own Fiorano JIT compiler is an example of this problem. As a state-of-the-art, RJIT compiler for Python, the Fiorano JIT compiler outperforms two other RJIT compilers (Unladen Swallow and Jython), but still shows a noticeable performance gap compared to PyPy, today's best performing Python JIT compiler. In this paper, we discuss techniques that have proved effective in the Fiorano JIT compiler as well as limitations of our current implementation. More importantly, this work offers the first in-depth look at benefits and limitations of the repurposed JIT compiler approach. We believe the most common pitfall of existing RJIT compilers is not focusing sufficiently on specialization, an abundant optimization opportunity unique to dynamically typed languages. Unfortunately, the lack of specialization cannot be overcome by applying traditional optimizations. José G. Castaños, David Edelsohn, Kazuaki Ishizaki, Priya Nagpurkar, Toshio Nakatani, Takeshi Ogasawara, Peng Wu 0001 |
OOPSLA | 1 |
| 2012 | Adding dynamically-typed language support to a statically-typed language compiler: performance evaluation, analysis, and tradeoffsabstractApplications written in dynamically typed scripting languages are increasingly popular for Web software development. Even on the server side, programmers are using dynamically typed scripting languages such as Ruby and Python to build complex applications quickly. As the number and complexity of dynamically typed scripting language applications grows, optimizing their performance is becoming important. Some of the best performing compilers and optimizers for dynamically typed scripting languages are developed entirely from scratch and target a specific language. This approach is not scalable, given the variety of dynamically typed scripting languages, and the effort involved in developing and maintaining separate infrastructures for each. In this paper, we evaluate the feasibility of adapting and extending an existing production-quality method-based Just-In-Time (JIT) compiler for a language with dynamic types. Our goal is to identify the challenges and shortcomings with the current infrastructure, and to propose and evaluate runtime techniques and optimizations that can be incorporated into a common optimization infrastructure for static and dynamic languages. We discuss three extensions to the compiler to support dynamically typed languages: (1) simplification of control flow graphs, (2) mapping of memory locations to stack-allocated variables, and (3) reduction of runtime overhead using language semantics. We also propose four new optimizations for Python in (2) and (3). These extensions are effective in reduction of compiler working memory and improvement of runtime performance. We present a detailed performance evaluation of our approach for Python, finding an overall improvement of 1.69x on average (up to 2.74x) over our JIT compiler without any optimization for dynamically typed languages and Python. Kazuaki Ishizaki, Takeshi Ogasawara, José G. Castaños, Priya Nagpurkar, David Edelsohn, Toshio Nakatani |
VEE | 3 |
| 2009 | Efficient, portable implementation of asynchronous multi-place programsabstractThe X10 programming language is organized around the notion of places (an encapsulation of data and activities operating on the data), partitioned global address space (PGAS), and asynchronous computation and communication. Ganesh Bikshandi, José G. Castaños, Sreedhar B. Kodali, V. Krishna Nandivada, Igor Peshansky, Vijay A. Saraswat, Sayantan Sur, Pradeep Varma, Tong Wen |
PPoPP | 2 |
| 2008 | Evaluating the effect of replacing CNK with linux on the compute-nodes of blue gene/labstractThe Blue Gene machines in production today run a small single-user, single-process kernel (CNK) having a limited functionality. Motivated by the desire to provide applications with a much richer operating environment, we evaluate the effect of replacing CNK with a standard Linux kernel on the compute nodes of Blue Gene/L. We show that with a relatively small amount of effort we were able to improve benchmark performance under Linux up to a level that is comparable to CNK. Edi Shmueli, Gheorghe Almási 0001, José R. Brunheroto, José G. Castaños, Gábor Dózsa, Sameer Kumar 0001, Derek Lieber |
ICS | 4 |
| 2006 | High performance file I/O for the Blue Gene/L supercomputerabstractParallel I/O plays a crucial role for most data-intensive applications running on massively parallel systems like Blue Gene/L that provides the promise of delivering enormous computational capability. We designed and implemented a highly scalable parallel file I/O architecture for Blue Gene/L, which leverages the benefit of the hierarchical and functional partitioning design of the system software with separate computational and I/O cores. The architecture exploits the scalability aspect of GPFS (General Parallel File System) at the backend, while using MPI I/O as an interface between the application I/O and the file system. We demonstrate the impact of our high performance I/O solution for Blue Gene/L with a comprehensive evaluation that consists of a number of widely used parallel I/O benchmarks and I/O intensive applications. Our design and implementation is not only able to deliver at least one order of magnitude speed up in terms of I/O bandwidth for a real-scale application HOMME (achieving aggregate bandwidth of 1.8 GB/Sec and 2.3 GB/Sec for write and read accesses, respectively), but also supports high-level parallel I/O data interfaces such as parallel HDF5 and parallel NetCDF scaling up to a large number of processors. Hao Yu 0008, Ramendra K. Sahoo, C. Howson, Gheorghe Almási 0001, José G. Castaños, Manish Gupta 0002, José E. Moreira, Jeff Parker, Thomas Engelsiepen, Robert B. Ross, Rajeev Thakur, Robert Latham, William Gropp |
HPCA | 5 |
| 2006 | Blue Gene system software - Design and implementation of a one-sided communication interface for the IBM eServer Blue Gene® supercomputerabstractThis paper discusses the design and implementation of a one-sided communication interface for the IBM Blue Gene/L supercomputer. This interface facilitates ARMCI and the Global Arrays toolkit and can be used by other one-sided communication libraries. New protocols, interrupt driven communication, and compute node kernel enhancements were required to enable these libraries. Three possible methods for enabling ARMCI on the Blue Gene/L software stack are discussed. A detailed look into the development process shows how the implementation of the one-sided communication interface was completed. This was accomplished on a compressed time scale with the collaboration of various organizations within IBM and open source communities. In addition to enabling the one-sided libraries, bandwidth enhancements were made for communication along a diagonal on the Blue Gene/L torus network. The maximum bandwidth improved by a factor of three. This work will enable a variety of one-sided applications to run on Blue Gene/L. Michael Blocksome, Charles Archer, Todd Inglett, Patrick McCarthy, Michael B. Mundy, Joe Ratterman, A. Sidelnik, Brian E. Smith, Gheorghe Almási 0001, José G. Castaños, Derek Lieber, José E. Moreira, Sriram Krishnamoorthy, Vinod Tipparaju, Jarek Nieplocha |
SC | 10 |
| 2006 | Blue Gene system software - Designing a highly-scalable operating system: the Blue Gene/L storyabstractBlue Gene/L is currently the world's fastest and most scalable supercomputer. It has demonstrated essentially linear scaling all the way to 131,072 processors in several benchmarks and real applications. The operating systems for the compute and I/O nodes of Blue Gene/L, are among the components responsible for that scalability. Compute nodes are dedicated to running application processes, whereas I/O nodes are dedicated to performing system functions. The operating systems adopted for each of these nodes reflect this separation of function. Compute nodes run a lightweight operating system called the compute node kernel. I/O nodes run a port of the Linux operating system. This paper discusses the architecture and design of this solution for Blue Gene/L in the context of the hardware characteristics that led to the design decisions. It also explains and demonstrates how those decisions are instrumental in achieving the performance and scalability for which Blue Gene/L is famous. José E. Moreira, Michael Brutman, José G. Castaños, Thomas Engelsiepen, Mark Giampapa, Thomas Gooding, Roger L. Haskin, Todd Inglett, Derek Lieber, Patrick McCarthy, Michael B. Mundy, Jeff Parker, Brian P. Wallenfelt |
SC | 3 |
| 2004 | Implementing MPI on the BlueGene/L Supercomputer
Gheorghe Almási 0001, Charles Archer, José G. Castaños, C. Christopher Erway, Philip Heidelberger, Xavier Martorell, José E. Moreira, Kurt W. Pinnow, Joe Ratterman, Nils Smeds, Burkhard D. Steinmacher-Burow, William Gropp, Brian R. Toonen |
Euro-Par | 3 |
| 2004 | Topic 3: Scheduling and Load Balancing
Emilio Luque, José G. Castaños, Evangelos P. Markatos, Raffaele Perego 0001 |
Euro-Par | 2 |
| 2003 | An Overview of the Blue Gene/L System Software Organization
Gheorghe Almási 0001, Ralph Bellofatto, José R. Brunheroto, Calin Cascaval, José G. Castaños, Luis Ceze, Paul Crumley, C. Christopher Erway, Joseph Gagliano, Derek Lieber, Xavier Martorell, José E. Moreira, Alda Sanomiya, Karin Strauss |
Euro-Par | 5 |
| 2002 | Blue Gene/L, a System-On-A-ChipabstractSummary form only given. Large powerful networks coupled to state-of-the-art processors have traditionally dominated supercomputing. As technology advances, this approach is likely to be challenged by a more cost-effective System-On-A-Chip approach, with higher levels of system integration. The scalability of applications to architectures with tens to hundreds of thousands of processors is critical to the success of this approach. Significant progress has been made in mapping numerous compute-intensive applications, many of them grand challenges, to parallel architectures. Applications hoping to efficiently execute on future supercomputers of any architecture must be coded in a manner consistent with an enormous degree of parallelism. The BG/L program is developing a peak nominal 180 TFLOPS (360 TFLOPS for some applications) supercomputer to serve a broad range of science applications. BG/L generalizes QCDOC, the first System-On-A-Chip supercomputer that is expected in 2003. BG/L consists of 65,536 nodes, and contains five integrated networks: a 3D torus, a combining tree, a Gb Ethernet network, barrier/global interrupt network and JTAG. George S. Almási, Daniel K. Beece, Ralph Bellofatto, Gyan Bhanot, Randy Bickford, Matthias A. Blumrich, Arthur A. Bright, José R. Brunheroto, Calin Cascaval, José G. Castaños, Luis Ceze, Paul Coteus, Siddhartha Chatterjee, Dong Chen 0005, George L.-T. Chiu, Thomas M. Cipolla, Paul Crumley, Alina Deutsch, Marc Boris Dombrowa, Wilm E. Donath, Maria Eleftheriou, Blake G. Fitch, Joseph Gagliano, Alan Gara, Robert S. Germain, Mark Giampapa, Manish Gupta 0002, Fred G. Gustavson, Shawn Hall, Ruud A. Haring, David F. Heidel, Philip Heidelberger, Lorraine M. Herger, Dirk Hoenicke, T. Jamal-Eddine, Gerard V. Kopcsay, Alphonso P. Lanzetta, Derek Lieber, M. Lu, Mark P. Mendell, Lawrence S. Mok, José E. Moreira, Ben J. Nathanson, Matthew Newton, Martin Ohmacht, Rick A. Rand, Richard D. Regan, Ramendra K. Sahoo, Alda Sanomiya, Eugen Schenfeld, Sarabjeet Singh, Peilin Song, Burkhard D. Steinmacher-Burow, Karin Strauss, Richard A. Swetz, Todd Takken, R. Brett Tremaine, Mickey Tsao, Pavlos Vranas, T. J. Christopher Ward, Michael E. Wazlowski, J. Brown, Thomas A. Liebsch, A. Schram, G. Ulsh |
CLUSTER | 10 |
| 2002 | Job Scheduling for the BlueGene/L System (Research Note)
Elie Krevat, José G. Castaños, José E. Moreira |
Euro-Par | 2 |
| 2002 | Evaluation of a Multithreaded Architecture for Cellular ComputingabstractCyclops is a new architecture for high-performance parallel computers that is being developed at the IBM T. J. Watson Research Center. The basic cell of this architecture is a single-chip SMP (symmetric multiprocessor) system with multiple threads of execution, embedded memory and integrated communications hardware. Massive intra-chip parallelism is used to tolerate memory and functional unit latencies. Large systems with thousands of chips can be built by replicating this basic cell in a regular pattern. In this paper, we describe the Cyclops architecture and evaluate two of its new hardware features: a memory hierarchy with a flexible cache organization and fast barrier hardware. Our experiments with the STREAM benchmark show that a particular design can achieve a sustainable memory bandwidth of 40 GB/s, equal to the peak hardware bandwidth and similar to the performance of a 128-processor SGI Origin 3800. For small vectors, we have observed in-cache bandwidth above 80 GB/s. We also show that the fast barrier hardware can improve the performance of the Splash-2 FFT kernel by up to 10%. Our results demonstrate that the Cyclops approach of integrating a large number of simple processing elements and multiple memory banks in the same chip is an effective alternative for designing high-performance systems. Calin Cascaval, José G. Castaños, Luis Ceze, Monty Denneau, Manish Gupta 0002, Derek Lieber, José E. Moreira, Karin Strauss, Henry S. Warren Jr. |
HPCA | 2 |
| 2002 | Job Scheduling for the BlueGene/L System
Elie Krevat, José G. Castaños, José E. Moreira |
JSSPP | 2 |
| 2002 | An overview of the BlueGene/L SupercomputerabstractThis paper gives an overview of the BlueGene/L Supercomputer. This is a jointly funded research partnership between IBM and the Lawrence Livermore National Laboratory as part of the United States Department of Energy ASCI Advanced Architecture Research Program. Application performance and scaling studies have recently been initiated with partners at a number of academic and government institutions,including the San Diego Supercomputer Center and the California Institute of Technology. This massively parallel system of 65,536 nodes is based on a new architecture that exploits system-on-a-chip technology to deliver target peak processing power of 360 teraFLOPS (trillion floating-point operations per second). The machine is scheduled to be operational in the 2004-2005 time frame, at price/performance and power consumption/performance targets unobtainable with conventional architectures. Narasimha R. Adiga, Gheorghe Almási 0001, George S. Almási, Yariv Aridor, Rajkishore Barik, Daniel K. Beece, Ralph Bellofatto, Gyan Bhanot, Randy Bickford, Matthias A. Blumrich, Arthur A. Bright, José R. Brunheroto, Calin Cascaval, José G. Castaños, Waiman Chan, Luis Ceze, Paul Coteus, Siddhartha Chatterjee, Dong Chen 0005, George L.-T. Chiu, Thomas M. Cipolla, Paul Crumley, K. M. Desai, Alina Deutsch, Tamar Domany, Marc Boris Dombrowa, Wilm E. Donath, Maria Eleftheriou, C. Christopher Erway, J. Esch, Blake G. Fitch, Joseph Gagliano, Alan Gara, Rahul Garg 0001, Robert S. Germain, Mark Giampapa, Balaji Gopalsamy, John A. Gunnels, Manish Gupta 0002, Fred G. Gustavson, Shawn Hall, Ruud A. Haring, David F. Heidel, Philip Heidelberger, Lorraine M. Herger, Dirk Hoenicke, R. D. Jackson, T. Jamal-Eddine, Gerard V. Kopcsay, Elie Krevat, Manish P. Kurhekar, Alphonso P. Lanzetta, Derek Lieber, L. K. Liu, M. Lu, Mark P. Mendell, A. Misra, Yosef Moatti, Lawrence S. Mok, José E. Moreira, Ben J. Nathanson, Matthew Newton, Martin Ohmacht, Adam J. Oliner, Vinayaka Pandit, R. B. Pudota, Rick A. Rand, Richard D. Regan, Bradley Rubin, Albert E. Ruehli, Silvius Vasile Rus, Ramendra K. Sahoo, Alda Sanomiya, Eugen Schenfeld, M. Sharma, Edi Shmueli, Sarabjeet Singh, Peilin Song, Vijay Srinivasan, Burkhard D. Steinmacher-Burow, Karin Strauss, Christopher W. Surovic, Richard A. Swetz, Todd Takken, R. Brett Tremaine, Mickey Tsao, Arun R. Umamaheshwaran, P. Verma, Pavlos Vranas, T. J. Christopher Ward, Michael E. Wazlowski, W. Barrett, C. Engel, B. Drehmel, B. Hilgart, D. Hill, F. Kasemkhani, David J. Krolak, Chun-Tao Li 0001, Thomas A. Liebsch, James A. Marcella, A. Muff, A. Okomo, M. Rouse, A. Schram, M. Tubbs, G. Ulsh, Charles D. Wait, J. Wittrup, Myung Bae, Kenneth A. Dockser, Lynn Kissel, Mark K. Seager, Jeffrey S. Vetter, K. Yates |
SC | 14 |
| 2001 | Demonstrating the scalability of a molecular dynamics application on a Petaflop computerabstractThe IBM Blue Gene project has endeavored into the development of a cellular architecture computer with millions of concurrent threads of execution. One of the major challenges of this project is demonstrating that applications can successfully exploit this massive amount of parallelism. Starting from the sequential version of a well known molecular dynamics code, we developed a new application that exploits the multiple levels of parallelism in the Blue Gene cellular architecture. We perform both analytical and simulation studies of the behavior of this application when executed on a very large number of threads. As a result, we demonstrate that this class of applications can execute efficiently on a large cellular machine. George S. Almási, Calin Cascaval, José G. Castaños, Monty Denneau, Wilm E. Donath, Maria Eleftheriou, Mark Giampapa, C. T. Howard Ho, Derek Lieber, José E. Moreira, Dennis M. Newns, Marc Snir, Henry S. Warren Jr. |
ICS | 3 |
| 2000 | Repartitioning Unstructured Adaptive MeshesabstractWe present a new parallel repartitioning algorithm for adaptive finite-element meshes that significantly reduces the amount of data that needs to move between processors in order to rebalance a workload after mesh adaptation (refinement or coarsening). These results derive their importance from the fact that the time to migrate data can be a large fraction of the total time far the parallel adaptive solution of partial differential equations. José G. Castaños, John E. Savage |
IPDPS | 1 |
| 1999 | PARED: A Framework for the Adaptive Solution of PDEsabstractDescribes our experience using PARED, an object-oriented system for the adaptive solution of partial differential equations (PDEs) in a distributed computing environment. PARED handles selective mesh refinement and coarsening, mesh repartitioning for load balancing and interprocessor mesh migration. PARED is an object-oriented system that runs on distributed memory parallel computers such as the IBM SP and networks of workstations. In this paper, we report on the use of PARED to solve 2D and 3D PDEs. We show that our object-oriented technology provides great flexibility with a small overhead to support the highly desirable adaptive features of PARED. José G. Castaños, John E. Savage |
HPDC | 1 |