VLDB 2026 Research / reviewers in the wild / expert
Joseph Kljaich Jr.
dblp:74/4412
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 1989
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 50% Hardware reliability and fault tolerance · 50% | |
| Theoretical computer science
1 paper |
Automated reasoning and model checking · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware reliability and fault tolerance
fault tolerance verification |
0.0 | 1 | 1989 | Formal Verification of Fault Tolerance Using Theorem-Proving Techniques · IEEE Trans. Computers 1989 |
Electronic design automation › hardware verification and test
formal verification |
0.0 | 1 | 1984 | A formal design verification system based on an automated reasoning system · DAC 1984 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 1984 | A formal design verification system based on an automated reasoning system · DAC 1984 |
Automated reasoning and model checking
theorem proving |
0.0 | 1 | 1989 | Formal Verification of Fault Tolerance Using Theorem-Proving Techniques · IEEE Trans. Computers 1989 |
Methods — techniques the papers use, named apart from their topics
theorem proving · 0.0petri net representation · 0.0automated reasoning · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1989 | Formal Verification of Fault Tolerance Using Theorem-Proving TechniquesabstractA formal verification system based on the use of automated reasoning techniques is described to validate fault tolerance. An extended Petri net representation, called a flow net, is described together with the theorem-proving implementation of a rule-based system for manipulating system descriptions. Examples taken from the literature are used to illustrate the representation and the capabilities of the formal verification system under development.> Joseph Kljaich Jr., Brian T. Smith, Anthony S. Wojcik |
IEEE Trans. Computers | 1 |
| 1984 | A formal design verification system based on an automated reasoning system
Anthony S. Wojcik, Joseph Kljaich Jr., Nagendra C. E. Srinivas |
DAC | 2 |