We have developed a completely automated approach to hardware design based on integrating three core technologies into one comprehensive system, namely genetic programming (GP), the VHSIC Hardware Description Language (VHDL) and field programmable gate arrays (FPGAs). Our system uses an automated GP engine, as opposed to a human designer, to evolve a hardware design composed of one or more FPGAs that will maximally achieve an application's software requirements. Several variants of our system exist; other variants are currently under development. The focus of this paper is to describe our original system design and its most recent revision to date.

We present a robust scalable parallelization of a multitarget tracking algorithm developed for air traffic surveillance. We couple the state estimation and data association problems by embedding an interacting multiple model (IMM) state estimator into an optimization-based assignment framework. A SPMD distributed-memory parallelization is described wherein the interface to the optimization problem, namely computing the rather numerous gating and IMM state estimates, covariance calculations, and likelihood function evaluations (used as cost coefficients in the assignment problem), is parallelized. We describe several heuristic algorithms developed for the inherent task allocation problem wherein the problem is one of assigning track tasks, having uncertain processing costs and negligible communication costs, across a set of homogeneous processors to minimize workload imbalances. Using a measurement database based on two FAA air traffic central radars, courtesy of Rome Laboratory, we show that near linear speedups are obtainable on a 32-node Intel Paragon supercomputer using simple task allocation algorithms.