SUMMARY: Third-generation genome sequencing technologies have led to a sharp increase in the number of high-quality genome assemblies. This allows the comparison of multiple assembled genomes of individual species and demands new tools for visualizing their structural properties. Here, we present plotsr, an efficient tool to visualize structural similarities and rearrangements between genomes. It can be used to compare genomes on chromosome level or to zoom in on any selected region. In addition, plotsr can augment the visualization with regional identifiers (e.g. genes or genomic markers) or histogram tracks for continuous features (e.g. GC content or polymorphism density). AVAILABILITY AND IMPLEMENTATION: plotsr is implemented as a python package and uses the standard matplotlib library for plotting. It is freely available under the MIT license at GitHub (https://github.com/schneebergerlab/plotsr) and bioconda (https://anaconda.org/bioconda/plotsr). SUPPLEMENTARY INFORMATION: Supplementary data are available at Bioinformatics online.

Genome assembly is one of the most important problems in computational genomics. Here, we suggest addressing the scaffolding phase, in which contigs need to be linked and ordered to obtain larger pseudo-chromosomes, by means of a second incomplete assembly of a related species. The idea is to use alignments of binned regions in one contig to find the most homologous contig in the other assembly. We show that ordering the contigs of the other assembly can be expressed by a new string problem, the longest run subsequence problem (LRS). We show that LRS is NP-hard and present reduction rules and two algorithmic approaches that, together, are able to solve large instances of LRS to provable optimality. In particular, they can solve realistic instances resulting from partial Arabidopsis thaliana assemblies in short computation time. Our source code and all data used in the experiments are freely available.

In hardware virtualization a hypervisor provides multiple Virtual Machines (VMs) on a single physical system, each executing a separate operating system instance. The hypervisor schedules execution of these VMs much as the scheduler in an operating system does, balancing factors such as fairness and I/O performance. As in an operating system, the scheduler may be vulnerable to malicious behavior on the part of users seeking to deny service to others or maximize their own resource usage. Recently, publically available cloud computing services such as Amazon EC2 have used virtualization to provide customers with virtual machines running on the provider's hardware, typically charging by wall clock time rather than resources consumed. Under this business model, manipulation of the scheduler may allow theft of service at the expense of other customers, rather than merely re-allocating resources within the same administrative domain. We describe a flaw in the Xen scheduler allowing virtual machines to consume almost all CPU time, in preference to other users, and demonstrate kernel-based and user-space versions of the attack. We show results demonstrating the vulnerability in the lab, consuming as much as 98% of CPU time regardless of fair share, as well as on Amazon EC2, where Xen modifications protect other users but still allow theft of service (following the responsible disclosure model, we have reported this vulnerability to Amazon; they have since implemented a fix that we have tested and verified). We provide a novel analysis of the necessary conditions for such attacks, and describe scheduler modifications to eliminate the vulnerability. We present experimental results demonstrating the effectiveness of these defenses while imposing negligible overhead. Also, cloud providers such as Amazon's EC2 do not explicitly reveal the mapping of virtual machines to physical hosts [in: ACM CCS, 2009]. Our attack itself provides a mechanism for detecting the co-placement of VMs, which in conjunction with appropriate algorithms can be utilized to reveal this mapping. Other cloud computing attacks may use this mapping algorithm to detect the placement of victims.

High performance hardware FFTs have numerous applications in instrumentation and communication systems. This paper describes a new parallel FFT architecture which combines the split-radix algorithm with a constant geometry interconnect structure. The split-radix algorithm is known to have lower multiplicative complexity than both radix-2 and radix-4 algorithms. However, it conventionally involves an “L-shaped” butterfly datapath whose irregular shape has uneven latencies and makes scheduling difficult. This work proposes a split-radix datapath that avoids the L-shape. With this, the split-radix algorithm can be mapped onto a constant geometry interconnect structure in which the wiring in each FFT stage is identical, resulting in low multiplexing overhead. Further, we exploit the lower arithmetic complexity of split-radix to lower dynamic power, by gating the multipliers during trivial multiplications. The proposed FFT achieves 46% lower power than a parallel radix-4 design at 4.5GS/s when computing a 128-point real-valued transform.

In deep sub-micron processes, on-chip interconnect is becoming the delay bottleneck and predominant source of power consumption. Simultaneous switching of large buses pose a great challenge on peak current as well. In this paper, we present a novel bus coding technique, based on transition pattern codes (TPC), to perform joint optimization. A TPC scheme has been constructed employing a joint cost function on energy and peak current. The encoder and decoder of the code has been synthesized using a commercial 28nm process and the power, delay and area overhead has been evaluated. HSPICE simulations in 28nm show up to 70% reduction in peak current and 15% reduction in energy consumption compared to an uncoded bus.

Recently, cloud computing services such as Amazon EC2 have used virtualization to provide customers with virtual machines running on the provider's hardware, typically charging by wall clock time rather than resources consumed. Under this business model, manipulation of the scheduler may allow theft-of-service at the expense of other customers. We have discovered and implemented an attack scenario which when implemented on Amazon EC2 allowed virtual machines to consume more CPU time regardless of fair share. We provide a novel analysis of the necessary conditions for such attacks, and describe scheduler modifications to eliminate the vulnerability. We present experimental results demonstrating the effectiveness of these defenses while imposing negligible overhead. Cloud providers such as Amazon's EC2 do not explicitly provide the mapping of VMs to physical hosts. Our attack itself provides a mechanism for detecting the co-placement of VMs, which in conjunction with appropriate algorithms can be utilized to reveal this mapping. We abstract mapping discovery as a problem of finding an unknown partition (i.e. of VMs among physical hosts) using a minimum number of co-location queries. We present an algorithm that is provably optimal when the maximum partition size is bounded. In the unbounded case we show upper and lower bounds using the probabilistic method in conjunction with a sieving technique. Our work has implications beyond this attack, for other cases of system and network topology inference from limited data.

In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless systems. To support various 4G standards, a configurable multi-mode MAP (maximum a posteriori) decoder is designed for both binary and duo-binary turbo codes with small resource overhead (less than 10%) compared to the single-mode architecture. To achieve high data rates in 4G, we present a parallel turbo decoder architecture with scalable parallelism tailored to the given throughput requirements. High-level parallelism is achieved by employing contention-free interleavers. Multi-banked memory structure and routing network among memories and MAP decoders are designed to operate at full speed with parallel interleavers. We designed a very low-complexity recursive on-line address generator supporting multiple interleaving patterns, which avoids the interleaver address memory. Design trade-offs in terms of area and power efficiency are explored to find the optimal architectures. A 711 Mbps data rate is feasible with 32 Radix-4 MAP decoders running at 200 MHz clock rate.

This paper presents an implementation-oriented breadth-first tree search MIMO detector design solution. Techniques at algorithm and VLSI architecture levels are developed to improve the implementation efficiency. Using Synopsys synthesis tool with 0.13 /spl mu/m CMOS technology, we designed soft-output detectors for 4 /spl times/ 4 MIMO channel with 64-QAM modulation. With the silicon areas less than 15 mm/sup 2/, the detectors can achieve up to about 80 Mbps and realize the performance very close to detectors using the sphere decoding algorithm.

Teleoperated robots in harsh environments have a significant likelihood of failures. It has been shown in previous work that a common type of failure such as that of a joint "locking up," when unidentified by the robot controller, can cause considerable performance degradation in the local behavior of the manipulator even for simple point-to-point motion tasks. The effects of a failure become more critical for a system with a human in the loop, where unpredictable behavior of the robotic arm can completely disorient the operator. In this experimental study involving teleoperation of a graphically simulated kinematically redundant manipulator, two control schemes, the pseudoinverse and a proposed failure-tolerant inverse, were randomly presented under both nonfailure and failure scenarios to a group of operators. Based on performance measures derived from the recorded trajectory data and operator ratings of task difficulty, it is seen that the failure-tolerant inverse kinematic control scheme improved the performance of the human/robot system.

Presented in this paper are energy-optimum reconfiguration strategies for channel codecs. These strategies are derived by solving an optimization problem, which has energy consumption as the objective function and a constraint on the bit error-rate (BER). Energy consumption models for a reconfigurable Reed-Solomon (RS) codec are derived via gate-level simulation of the finite field arithmetic modules. These energy models along with the BER expressions are then employed to derive the energy-optimum reconfiguration strategies. The energy savings are computed by comparing the energy consumption of the reconfigurable codec with that of the static codec. The energy savings range from 0%-83% for channel signal-to-noise ratio (SNR) variations from 7 dB-10 dB. On an average 55% energy savings are achieved.

The use of robots in hostile environments significantly increases the likelihood of failures in the robot's subsystems. Existing techniques for developing failure tolerant robots rely on effective failure detection and identification. Since failure identification is itself a difficult process that may not always be successful, it is important to consider the behavior of the robot prior to identification of a fault, or even the possibility of failures remaining unidentified. This work proposes control strategies that improve local measures of failure tolerance for kinematically redundant robots experiencing unidentified locked-joint failures. Measures to evaluate the fault tolerance capability of the various schemes are presented and the performance of the proposed schemes are demonstrated with an example.

Teleoperated robots in harsh environments have a significant likelihood of failures. A common type of failure such as that of a joint "locking up", when unidentified by the robot controller, can cause considerable performance degradation in the local behavior of the manipulator even for simple point-to-point motion tasks. The effects of a failure become more critical for a system with a human in the loop, where unpredictable behavior of the robotic arm can completely disorient the operator. In this experimental study involving teleoperation of a graphically simulated kinematically redundant manipulator, two control schemes, the pseudo-inverse and a proposed failure-tolerant inverse, were randomly presented under both non-failure and failure scenarios to a group of operators. Based on the performance measures derived from the recorded trajectory data and operator responses, it is seen that the failure-tolerant inverse kinematic control scheme improved the performance of the human/robot system.

In this paper, dynamic algorithm transformations (DATs) for designing low-power reconfigurable signal-processing systems are presented. These transformations minimize energy dissipation while maintaining a specified level of mean squared error or signal-to-noise ratio. This is achieved by modeling the nonstationarities in the input as temporal/spatial transitions between states in the input state-space. The reconfigurable hardware fabric is characterized by its configuration state-space. The configurable parameters are taken to be the filter taps, coefficient and data precisions, and supply voltage V/sub dd/. An energy-optimal reconfiguration strategy is derived as a mapping from the input to the configuration state-space. In this strategy, taps are powered down starting with the tap with the smallest value [w/sub k//sup 2///spl Sigma//sub m/(w/sub k/)] (where w/sub k/ and /spl Sigma//sub m/(w/sub k/) are, respectively, the adders, redundant-to-binary conversion, tree adders, coefficient and energy dissipation of the kth tap). Optimal values for precision and supply voltage V/sub dd/ are subsequently computed from the roundoff error and critical path delay requirements, respectively. The DAT-based adaptive filter is employed as a near-end crosstalk (NEXT) canceller in a 155.52-Mb/s asynchronous transfer mode-local area network transceiver over category-3 wiring. Simulation results indicate that the energy savings range from -2% to 87% as the cable length varies from 110 to 40 m, respectively, with an average saving of 69%. An average saving of 62% is achieved for the case where the supply voltage V/sub dd/ is kept fixed.

Presented in this paper are dynamic algorithm transformations (DAT) for systematic design of reconfigurable computing engines. These techniques allow dynamic alteration of algorithm properties in response to input non-stationarities. The input is modeled as a set of states with an underlying probability distribution, /spl Pscr//sub S/. For each input state s, a signal monitoring algorithm (SMA) computes a power-optimal configuration for the signal processing algorithm (SPA) block. A fraction /spl alpha/ of the (SPA) block is hardwired and the remaining (1-/spl alpha/) is reconfigurable. Similarly, the (SMA) block computation is partitioned into a fraction /spl beta/ for the memory and the remaining (1-/spl beta/) for the data path. For the given input state distribution, the optimal values of /spl alpha/ (/spl alpha//sub opt/) and /spl beta/ (/spl beta//sub opt/) are determined. It is shown that for frequency selective filtering (FIR filters), the power savings of 35%-45% can be achieved by a DAT-based reconfigurable system as compared to the traditional design based on the worst-case scenario.

Robots are frequently used for operations in hostile environments. The very nature of these environments, however, increases the likelihood of robot failures. Common failure tolerance techniques rely on effective failure detection. Since a failure may not always be successfully detected, or even if detected, may not be detected soon enough, it becomes important to consider the behavior of manipulators with undetected failures. This work focuses on developing techniques to analyse a manipulator's workspace and identify regions in which tasks, characterized by sequences of point-to-point moves, can be completed even with such failures. Measures of fault tolerance are formulated to allow for the evaluation of the workspace.

Due to high data rates and limited bandwidth as well as limited battery power, wireless multimedia communications systems must be optimized in every possible way. We develop a generic matching scheme for wireless image and video communication in which the three most significant components: the source coder, the channel coder, and hardware power consumption, are jointly optimized. That is, we maximize the end-to-end image quality subject to a total power constraint on both the RF transmission power and the power consumption of the digital implementation of the channel coder, which represents a major portion of the total hardware power in short-range applications.

Operations in hazardous or remote environments are invariably performed by robots. The hostile nature of the environments, however, increase the likelihood of failures for robots used in such applications. The difficulty and delay in the detection and consequent correction of these faults makes the post-fault performance of the robots particularly important. This work investigates the behavior of robots experiencing undetected locked-joint failures in a general class of tasks characterized by point-to-point motion. The robot is considered to have "converged" to a task position and orientation if all its joints come to rest when the end-effector is at that position. It is seen that the post-fault behavior may be classified into three categories: (1) the robot converges to the task position; (2) the robot converges to a position other than the task position; or (3) the robot does not converge, but keeps moving forever. The specific conditions for convergence are identified, and the different behaviors illustrated with examples of simple planar manipulators.

Article Free Access Share on Dynamic algorithm transformation (DAT) for low-power adaptive signal processing Authors: Manish Goel Coordinated Science Lab./ECE Department, Univ. of Illinois at Urbana-Champaign, 1308 W. Main Street, Urbana IL Coordinated Science Lab./ECE Department, Univ. of Illinois at Urbana-Champaign, 1308 W. Main Street, Urbana ILView Profile , Naresh R. Shanbhag Coordinated Science Lab./ECE Department, Univ. of Illinois at Urbana-Champaign, 1308 W. Main Street, Urbana IL Coordinated Science Lab./ECE Department, Univ. of Illinois at Urbana-Champaign, 1308 W. Main Street, Urbana ILView Profile Authors Info & Claims ISLPED '97: Proceedings of the 1997 international symposium on Low power electronics and designAugust 1997 Pages 161–166https://doi.org/10.1145/263272.263316Published:01 August 1997Publication History 1citation181DownloadsMetricsTotal Citations1Total Downloads181Last 12 Months2Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Low-power and high-speed algorithms and architectures for complex adaptive filters are presented in this paper. These architectures have been derived via the application of algebraic and algorithm transformations. The strength reduction transformation when applied at the algorithmic level results in a power reduction by 21% as compared to the traditional cross-coupled structure. A fine-grain pipelined architecture is then developed via the relaxed look-ahead transformation. The pipelined architecture allows high-speed operation with minimum overhead and when combined with power-supply reduction enables additional power-savings of 40-69%. Thus, an overall power-saving of 60-90% over the traditional cross-coupled architecture is achieved.