Demo Data from VLDB 2026 / reviewers in the wild / expert
Jörg Kramer
dblp:74/5251
· DBLP profile ↗
9ranked-venue papers
2as first author
0since 2021 · last 2004
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Artificial intelligence and machine learning · 7 · 1 first-authorSystems, architecture and hardware · 1 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
5 papers |
Emerging computing paradigms · 56% Integrated circuit design · 41% Hardware accelerators and domain-specific architectures · 3% | |
| Artificial intelligence
2 papers |
Representation and self-supervised learning · 84% Robot navigation and mapping · 16% | |
| Computer graphics and multimedia
2 papers |
Image and video processing · 100% |
Topics — the 8 heaviest of 12, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design › analog and mixed-signal circuits
analog VLSI |
0.1 | 4 | 2004 | The Cerebellum Chip: an Analog VLSI Implementation of a Cerebellar Model of Classical Conditioning · NIPS 2004 Orientation-Selective aVLSI Spiking Neurons · NIPS 2001 Analog VLSI architectures for motion processing: from fundamental limits to system applications · Proc. IEEE 1996 |
Emerging computing paradigms
neuromorphic computing |
0.1 | 3 | 2004 | The Cerebellum Chip: an Analog VLSI Implementation of a Cerebellar Model of Classical Conditioning · NIPS 2004 Orientation-Selective aVLSI Spiking Neurons · NIPS 2001 Parallel analog VLSI architectures for computation of heading direction and time-to-contact · NIPS 1995 |
Emerging computing paradigms
neuromorphic hardware |
0.0 | 1 | 2004 | The Cerebellum Chip: an Analog VLSI Implementation of a Cerebellar Model of Classical Conditioning · NIPS 2004 |
Machine learning › Representation and self-supervised learning › representation learning › dimensionality reduction › manifold learning
topographic maps |
0.0 | 1 | 2002 | Developing Topography and Ocular Dominance Using Two aVLSI Vision Sensors and a Neurotrophic Model of Plasticity · NIPS 2002 |
Image and video processing
motion estimation |
0.0 | 2 | 1996 | Analog VLSI architectures for motion processing: from fundamental limits to system applications · Proc. IEEE 1996 Compact Integrated Motion Sensor With Three-Pixel Interaction · IEEE Trans. Pattern Anal. Mach. Intell. 1996 |
Emerging computing paradigms › neuromorphic computing
spiking neural network |
0.0 | 1 | 2001 | Orientation-Selective aVLSI Spiking Neurons · NIPS 2001 |
Integrated circuit design › analog and mixed-signal circuits
mixed-signal circuit design |
0.0 | 1 | 1996 | Compact Integrated Motion Sensor With Three-Pixel Interaction · IEEE Trans. Pattern Anal. Mach. Intell. 1996 |
Hardware accelerators and domain-specific architectures
analog computing accelerator |
0.0 | 1 | 1995 | Parallel analog VLSI architectures for computation of heading direction and time-to-contact · NIPS 1995 |
Methods — techniques the papers use, named apart from their topics
analog VLSI · 0.1classical conditioning model · 0.1spike train correlation · 0.0aVLSI vision sensor · 0.0time-delay measurement · 0.0reichardt sensor · 0.0photoreceptor integration · 0.0gradient algorithm · 0.0correlation algorithm · 0.0adaptive time constant filter · 0.0winner-take-all · 0.0integrate-and-fire neuron · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2004 | The Cerebellum Chip: an Analog VLSI Implementation of a Cerebellar Model of Classical ConditioningabstractWe present a biophysically constrained cerebellar model of classical conditioning, implemented using a neuromorphic analog VLSI (aVLSI) chip. Like its biological counterpart, our cerebellar model is able to control adaptive behavior by predicting the precise timing of events. Here we describe the functionality of the chip and present its learning performance, as evaluated in simulated conditioning experiments at the circuit level and in behavioral experiments using a mobile robot. We show that this aVLSI model supports the acquisition and extinction of adaptively timed conditioned responses under real-world conditions with ultra-low power consumption. Constanze Hofstoetter, Manuel Gil, Kynan Eng, Giacomo Indiveri, Matti Mintz, Jörg Kramer, Paul F. M. J. Verschure |
NIPS | 6 |
| 2002 | Developing Topography and Ocular Dominance Using Two aVLSI Vision Sensors and a Neurotrophic Model of PlasticityabstractA neurotrophic model for the co-development of topography and ocular dominance columns in the primary visual cortex has recently been pro- posed. In the present work, we test this model by driving it with the output of a pair of neuronal vision sensors stimulated by disparate mov- ing patterns. We show that the temporal correlations in the spike trains generated by the two sensors elicit the development of refined topogra- phy and ocular dominance columns, even in the presence of significant amounts of spontaneous activity and fixed-pattern noise in the sensors. Terry Elliott, Jörg Kramer |
NIPS | 2 |
| 2002 | Coupling an aVLSI Neuromorphic Vision Chip to a Neurotrophic Model of Synaptic Plasticity: The Development of TopographyabstractWe couple a previously studied, biologically inspired neurotrophic model of activity-dependent competitive synaptic plasticity and neuronal development to a neuromorphic retina chip. Using this system, we examine the development and refinement of a topographic mapping between an array of afferent neurons (the retinal ganglion cells) and an array of target neurons. We find that the plasticity model can indeed drive topographic refinement in the presence of afferent activity patterns generated by a real-world device. We examine the resilience of the developing system to the presence of high levels of noise by adjusting the spontaneous firing rate of the silicon neurons. Terry Elliott, Jörg Kramer |
Neural Comput. | 2 |
| 2001 | Orientation-Selective aVLSI Spiking NeuronsabstractWe describe a programmable multi-chip VLSI neuronal system that can be used for exploring spike-based information processing models. The system consists of a silicon retina, a PIC microcontroller, and a transceiver chip whose integrate-and-fire neurons are connected in a soft winner-take-all architecture. The circuit on this multi-neuron chip ap- proximates a cortical microcircuit. The neurons can be configured for different computational properties by the virtual connections of a se- lected set of pixels on the silicon retina. The virtual wiring between the different chips is effected by an event-driven communication pro- tocol that uses asynchronous digital pulses, similar to spikes in a neu- ronal system. We used the multi-chip spike-based system to synthe- size orientation-tuned neurons using both a feedforward model and a feedback model. The performance of our analog hardware spiking model matched the experimental observations and digital simulations of continuous-valued neurons. The multi-chip VLSI system has advantages over computer neuronal models in that it is real-time, and the computa- tional time does not scale with the size of the neuronal network. Shih-Chii Liu, Jörg Kramer, Giacomo Indiveri, Tobi Delbruck, Rodney J. Douglas |
NIPS | 2 |
| 2001 | Orientation-selective aVLSI spiking neurons
Shih-Chii Liu, Jörg Kramer, Giacomo Indiveri, Tobi Delbruck, Thomas Burg, Rodney J. Douglas |
Neural Networks | 2 |
| 1996 | Compact Integrated Motion Sensor With Three-Pixel InteractionabstractAn integrated circuit with on-chip photoreceptors is described, that computes the bi-directional velocity of a visual stimulus moving along a given axis in the focal plane by measuring the time delay of its detection at two positions. Due to the compactness of the circuit, a dense array of such motion-sensing elements can be monolithically integrated to estimate the velocity field of an image and to extract higher-level image features through local or global interaction. Jörg Kramer |
IEEE Trans. Pattern Anal. Mach. Intell. | 1 |
| 1996 | Analog VLSI architectures for motion processing: from fundamental limits to system applicationsabstractThis paper discusses some of the fundamental issues in the design of highly parallel, dense, low-power motion sensors in analog VLSI. Since photoreceptor circuits are an integral part of all visual motion sensors, we discuss how the sizing of photosensitive areas can affect the performance of such systems. We review the classic gradient and correlation algorithms and give a survey of analog motion-sensing architectures inspired by them. We calculate how the measurable speed range scales with signal-to-noise ratio (SNR) for a classic Reichardt sensor with a fixed time constant. We show how this speed range may be improved using a nonlinear filter with an adaptive time constant, constructed out of a diode and a capacitor, and present data from a velocity sensor based on such a filter. Finally, we describe how arrays of such velocity sensors call be employed to compute the heading direction of a moving subject and to estimate the time-to-contact between the sensor and a moving object. Rahul Sarpeshkar, Jörg Kramer, Giacomo Indiveri, Christof Koch |
Proc. IEEE | 2 |
| 1995 | An Analog VLSI Velocity SensorabstractAn integrated circuit that computes the velocity vector of a visual stimulus in one dimension is presented. The circuit combines optical sensors and associated electronics on a single silicon chip, processed with standard CMOS technology. The velocity is inferred from the time delay of the appearance of an image feature at two fixed locations on the chip. The circuit operates quite robustly for high-contrast stimuli over considerable irradiance and velocity ranges. With lower-contrast stimuli the output signal for a given velocity tends to decrease, while the direction selectivity is still maintained. The individual motion-sensing cells are compact, and they are therefore suited for use in dense 1D or 2D imaging arrays. Jörg Kramer, Rahul Sarpeshkar, Christof Koch |
ISCAS | 1 |
| 1995 | Parallel analog VLSI architectures for computation of heading direction and time-to-contact
Giacomo Indiveri, Jörg Kramer, Christof Koch |
NIPS | 2 |