The detection and partitioning of standard cells from Scanning Electron Microscope (SEM) images is a crucial step in hardware assurance of Integrated Circuit (IC). Traditional methods may struggle with the noise and complexity of these signals. This paper introduces a novel approach to SEM image processing by framing the standard cell partition problem as a multiple hypothesis testing (MHT) problem. This method enables simultaneous decision-making across many hypotheses, enhancing detection accuracy while controlling the false discovery rate (FDR). We show how MHT can identify partition lines in noisy brightness signals extracted from SEM images. Using the Benjamini-Hochberg (BH) procedure, we achieve effective FDR control, improving detection robustness and providing a clearer understanding of cell structures. This study demonstrates the suitability of MHT for SEM image processing and its potential for other circuit-related challenges.

Automated inspection of Integrated Circuits (ICs) on Printed Circuit Boards (PCBs) is essential for ensuring the reliability of modern electronic systems. However, the inspection process faces significant challenges, particularly data scarcity and low inter-class variance. To address these challenges, we propose SSRNet, a few-shot learning-based framework for precise IC segmentation in complex PCB optical images. Unlike traditional deep learning models, our proposed SSRNet utilizes a similarity-guided approach for initial mask prediction and integrates a region classifier for further refinement. This design allows SSRNet to accurately segment IC components, even with limited annotated data. Experimental results demonstrate that our proposed SSRNet outperforms the state-of-the-art model, achieving a 23.0% increase in IoU and a 13.2% improvement in the Dice coefficient on NTU PCB DSX Dataset (NPDD).

Hardware Assurance (HA) of Integrated Circuit (IC) requires the extraction and analysis of circuit netlist from a manufactured or programmed IC (in the case of Field Programmable Gate Array (FPGA)). The first and most important step in this analysis is to detect Intellectual Property (IP) circuit(s) of interest from an extracted ‘sea-of-gates’ netlist. State-of-the-art approach involves converting the extracted netlist into a graph and using Graph Neural Network (GNN), a powerful machine-learning method on graphs for IP circuit detection. However, reported methods usually employed shallow GNNs with small receptive fields which are inadequate for detecting large and complete IP circuits. In this paper, we propose a novel GNN, coined Long-Short-GNN, which uniquely incorporates a Long-view Network (for global coarse-grained information) and a Short-view Network (for local fine-grained information) for FPGA IP circuit detection. By experiments on detecting a variety of large and complete FPGA IP circuits, we proved its efficacy. Specifically, on average, our proposed Long-Short-GNN outperformed all reported methods by a large margin of up to ~13.8% improvement on F1 Score.

Integrated Circuit (IC) verification is of paramount importance to the security of IC. The success of circuit verification largely depends on the correctness of the recovered circuit netlist from Scanning Electron Microscopic (SEM) images. Due to imperfections in imaging process and feature extraction process, the recovered circuit netlist usually contains connection errors. The corrections of these errors require tedious manual tracing of metal lines or are sometimes impossible due to the corrupt regions in SEM images. In this work, we perform error correction based on a connection heuristic in circuit. We propose MLConnect, a machine learning based connection prediction framework that captures the probabilities of gate connections in circuits. We further propose a post-processing technique to recover circuit connections based on gate connection probabilities and circuit rules. Our results show that the proposed MLConnect successfully recovered 80.87% of gate connections in erroneous circuits from ISCAS-85 benchmark suites. Our method can largely automate the process of circuit recovery.

Global distribution of the Integrated Circuit (IC) supply chain amplifies the importance of Hardware Assurance (HA), i.e., to ensure the integrity of manufactured IC. Standard cell recognition is a crucial step in HA, which is to identify the functionality of a standard cell based on its Scanning Electron Microscope (SEM) images. Conventionally, this is mostly done by human inspection, which is labor-intensive and error-prone. Current works on automating this process only work on the image domain and have sub-optimal performance due to the challenges incurred by the variation in the appearance of standard cells in the images. In this paper, we propose an automatic process for standard cell recognition, through conversion to a standardized graph representation and comparing the graph structure to identify the type of the standard cell. Our proposed method represents each unique circuit structure in a unique graph representation and thus enables a one-to-one matching to a known set of templates for functionality identification. Our experiments show that our proposed method can always recognize the standard cells correctly, even under the most challenaing scenario.

Overseas foundries pose potential threat to the integrity of manufactured ICs where malicious modifications, known as Hardware Trojans (HTs) may be inserted into the IC layout. To detect this, SEM images of manufactured ICs need to be compared with their original GDS images. However, existing methods either avoid direct comparison or are susceptible to errors due to the inherent differences in shapes between SEM images and GDS images. In this paper, we instead propose a Deep-Learning (DL)-based image transformation method, named SEM2GDS, which transforms a SEM image into its GDS image and produce shapes with sharp corners. This allows direct comparison between a transformed SEM image and the original GDS image for modification detection. By experiment on a set of SEM images and their corresponding GDS images, we demonstrate the efficacy of our proposed method. Our method is fast and able to achieve high detection accuracy, high f1 score, and very low False Negative Rate (FNR) of <0.02. Our method can detect real and small changes between SEM and GDS images.

While microscopy enables material scientists to view and analyze microstructures, the imaging results often include defects and anomalies with varied shapes and locations. The presence of such anomalies significantly degrades the quality of microscopy images and the subsequent analytical tasks. Comparing to classic feature-based methods, recent advancements in deep learning provide a more efficient, accurate, and scalable approach to detect and remove anomalies in microscopy images. However, most of the deep inpainting and anomaly detection schemes require a certain level of supervision, i.e., either annotation of the anomalies, or a corpus of purely normal data, which are limited in practice for supervision-starving microscopy applications. In this work, we propose a self-supervised deep learning scheme for joint anomaly detection and inpainting of microscopy images. The proposed anomaly detection model can be trained over a mixture of normal and abnormal microscopy images without any labeling. Instead of a two-stage scheme, our multi-task model can simultaneously detect abnormal regions and remove the defects via jointly training. To benchmark such microscopy application under the real-world setup, we propose a novel dataset of real microscopic images of integrated circuits, dubbed MIIC. The proposed dataset contains tens of thousands of normal microscopic images, while we labeled hundreds of them containing various imaging and manufacturing anomalies and defects for testing. Experiments show that the proposed model outperforms various popular or state-of-the-art competing methods for both microscopy image anomaly detection and inpainting.

Pattern recognition algorithms have recently been pursued for automatic analysis of delayered IC images, i.e. the detection of circuit components. Wide experimentation on the existing training-based approaches are hampered by heavy data labeling, expensive model training, or long processing time. In this paper, we propose a global template projection and matching (GTPM) method that requires no training and a minimal amount of data labeling for circuit component detection. Our proposed GTPM method achieves a higher or comparable accuracy as the reported approaches while being more computationally efficient.

We propose a novel asynchronous logic (async) quasi-delay-insensitive (QDI) sense-amplifier half-buffer (SAHB) cell design approach, with emphases on high operational robustness, high speed, and low power dissipation. There are five key features of our proposed SAHB. First, the SAHB cell embodies the async QDI 4-phase (4φ) signaling protocol to accommodate process-voltage-temperature variations. Second, the sense amplifier (SA) block in SAHB cells embodies a cross-coupled latch with a positive feedback mechanism to speed up the output evaluation. Third, the evaluation block in the SAHB comprises both nMOS pull-up and pull-down networks with minimum transistor sizing to reduce the parasitic capacitance. Fourth, both the evaluation block and SA block are tightly coupled to reduce redundant internal switching nodes. Fifth, the SAHB cell is designed in CMOS static logic and hence appropriate for full-range dynamic voltage scaling operation for VDDranging from nominal voltage (1 V) to subthreshold voltage (~0.3 V). When six library cells embodying our proposed SAHB are compared with those embodying the conventional async QDI precharged half-buffer (PCHB) approach, the proposed SAHB cells collectively feature simultaneous -.64% lower power, -.21% faster, and ~6% smaller IC area; the PCHB cell is inappropriate for subthreshold operation. A prototype 64-bit Kogge-Stone pipeline adder based on the SAHB approach (at 65 nm CMOS) is designed. For a 1-GHz throughput and at nominal VDD, the design based on the SAHB approach simultaneously features -.56% lower energy and -.24% lower transistor count advantages than its PCHB counterpart. When benchmarked against the ubiquitous synchronous logic counterpart, our SAHB dissipates -.39% lower energy at the 1-GHz throughput.

Although Total Ionizing Dose (TID) effects are generally unpronounced in deep-submicron-CMOS, we show the TID-induced leakage current @TID=500Krad is significant in NMOS-finger-transistors of GlobalFoundries 65nm CMOS. Further, Radiation-Hardening-By-Design techniques against said TID effect are recommended.

We comprehensively study three types of radiation-hardened flip-flops: DICE for SEU-hardening, temporal for SET-hardening, and Triple-Modular-Redundancy for SEU-cum-SET-hardening. Our study includes their trade-offs of circuit/radiation-hardness attributes. We find that DICE flip-flops remain the most competitive.

We propose a novel dynamic voltage scaling (DVS) pipeline with three significant attributes. First, it features a fine-grained DVS which innately attempts to power most of the circuits therein at low voltages, and when the speed is beneath the requirement, to scale up the voltage. Second, it supports fast-transition DVS within one-and-a-half clock duration per operation, and its operation remains error-free during that duration; we define such attribute as half-clock-tolerant. Third, it consists of a single power source (single-VDD) which supports three voltage scales (1.2V, 0.8V and 0.5V) for power/speed tradeoffs, and has standardized 1.2V output to seamlessly interface with other proposed/conventional pipelines. These attributes are achieved due to the embodiment of a DVS power unit, asynchronous building blocks to control/synchronize the operation, a dual-rail critical path to innately detect the completion of the operation, and level shifters to standardize the output voltage. We demonstrate our proposed pipeline by designing a multiplier embodied in a Fast Fourier Transform processor (@65nm CMOS). We show that the multiplier based on our proposed pipeline, on average, is 1.94× more power-efficient than that based on a conventional pipeline.

We describe a dual-core 8051 microcontroller system featuring the synchronous and asynchronous (clockless) mode of operation. The synchronous mode of operation is achieved by means of a synchronous 8051 microcontroller core, while the asynchronous mode of operation is achieved by means of an asynchronous 8051 microcontroller core. The 8051 microcontroller system features shared embedded program and data memories that enable the switching between the two microcontroller cores during program execution. The measured energy, speed and electromagnetic interference of both microcontroller cores will be compared at different operation workloads.

The robustness of asynchronous logic has proved useful in dealing with contemporary problems in CMOS design such as process variations and power management. However, the general cryptic nature of asynchronous logic has stymied the widespread acceptance of this alternate design technique. Fortunately, the semi-custom approach to asynchronous design reduces the tedious handcrafting efforts that are often non-trivial in large system-on-chips (SoCs). However, even with the adoption of this design approach requires careful selection of asynchronous templates that will suit overall system needs. Therefore in this paper, the most eminent Quasi-Delay-Insensitive asynchronous template families reported to date will be presented, and followed by an in-depth comparison of various design FOMs - template area, static/dynamic capacity, cycle time, latency, throughput and Et2. The most aggressive template (EESTFB) can reach a maximum throughput of 3.56Giga items/s on 0.13µm @ 1.2V.

We describe an asynchronous-logic (async) 16×16-bit pipelined multiplier based on our proposed Sense Amplifier-Based Pass Transistor Logic (SAPTL) with emphases on high energy-delay efficiency. The multiplier is targeted for an async multi-core System-On-Chip (SOC). This attribute is achieved by simplifying and optimizing the NMOS pass transistor stacks and decision-making C-element, therein to reduce the circuit area overheads and transistor switchings in SAPTL. Based on the simulations (@1V, 65nm CMOS process), the async 16×16-bit pipelined multiplier based on our proposed SAPTL approach features, on average, 31% shorter delay, 21% lower energy/operation achieving a total of 46% lower energy-delay product, and 16% lesser number of transistors when compared to the reported SAPTL approaches.

In this paper, a fine-grained power gating technique for an asynchronous-logic pipeline stage is proposed using locally controlled gating transistors. The proposed power gating technique is implemented with minimal control overheads (one additional inverter per pipeline stage for driving PMOS Gating) and delay overheads (within 15% more than the conventional asynchronous-logic pipeline stage). Different types of gating configurations using only PMOS transistor (PMOS Gating), only NMOS transistor (NMOS Gating), and both types of transistors (Dual Gating) are examined and compared. The effectiveness of the proposed power gating technique to the Combinational Block therein with different data input rates is investigated. Based on the computer simulation results, we have found that ≫70% wasted power reduction (including both short-circuit and leakage powers) as compared to the conventional asynchronous-logic pipeline stage can be achieved with all gating configurations. In particular, Dual Gating achieves the best wasted power reduction of 86% for short-circuit power and 99% for leakage power @ 10Mbps input rate.