The present work aims at developing a smart dental implant meant to restore the proprioceptive control of the masticatory muscle activity, in consequence of the loss of natural teeth. When periodontal afferent information is not available, the control of the occlusal forces is impaired and the capacity of regulating the masticatory force on a certain tooth or teeth is affected. The active implant being proposed detects the force exerted on teeth and proportionally generates stimuli to send that information to the brain in order to restore the neurobiological mechanisms associated to the masticatory sensory-motor function. After the description of the physiological and biomechanical aspects related to the loss of teeth and masticatory function, details are provided on the force sensing, processing and stimuli generation circuits included in the active implant being proposed. Preliminary simulation results that illustrate the implant functionality are presented.

A multifunctional router IC to be included in the nodes of a wearable body sensor network is described and evaluated. The router targets different application scenarios, especially those including tens of sensors, embedded into textile materials and with high data-rate communication demands. The router IC supports two different functionality sets, one for sensor nodes and another for the base node, both based on the same circuit module. The nodes are connected to each other by means of woven thick conductive yarns forming a mesh topology with the base node at the center. From the standpoint of the network, each sensor node is a four port router capable of handling packets from destination nodes to the base node, with sufficient redundant paths. The adopted hybrid circuit and packet switching scheme significantly improve network performance in terms of end-to-end delay, throughput and power consumption. The IC also implements a highly precise, sub-microsecond one-way time synchronization protocol which is used for time stamping the acquired data. The communication module was implemented in a 4-metal,$0.35~\mu \text{m}$CMOS technology. The maximum data rate of the system is 35 Mbps while supporting up to 250 sensors, which exceeds current BAN applications scenarios.

Wearable vital signals monitoring systems are promoting new assistance approaches in the healthcare system and are essential for the future connected health paradigm. The present work addresses the design of a cardiac and coronary monitoring system taking into consideration dependability and autonomy issues. A fuzzy logic approach is used to determine, in case deviations in the captured electrocardiogram are detected, whether these are occurring in the patient or in the system. As for autonomy, the use of data compression versus extra data processing balance is analysed to find operating conditions for which compression is worth to be used.

In this paper, a novel Bayesian model fusion (BMF) method is proposed for test cost reduction based on wafer-level spatial variation modeling. BMF relies on the assumption that a large number of wafers of the same circuit design (e.g., all wafers from the same lot) share a similar spatial pattern. Hence, the measurement data from one wafer can be borrowed to model the spatial variation of other wafers via Bayesian inference. By applying the Sherman-Morrison-Woodbury formula, a fast numerical algorithm is derived to reduce the computational cost of BMF for practical test applications. Furthermore, a new test methodology is developed based on BMF and it closely monitors the escape rate and yield loss. As is demonstrated by the wafer probe measurement data of an industrial RF transceiver, BMF achieves 1.125× reduction in test cost and 2.6× reduction in yield loss, compared to the conventional approach based on virtual probe (VP).

Different built-in self testing schemes for RF circuits have been developed resorting to peak voltage detectors. These are simple to implement but provide a conditional RF power measurement accuracy as impedance is assumed to be known. A true power detector is presented which allows obtaining more accurate measurements, namely as far as output load variations are concerned. The theoretical fundaments underlining the power detector operating principle are presented and simulation and experimental results obtained with a prototype chip are described which confirm the benefits of measuring true power, comparing to output peak voltage, when observing output load matching deviations and complex waveforms.

This paper describes the design of a processor specific for testing cores embedded in system-on-chip. This processor, which can be implemented within a system's reconfigurable area, shall be responsible for scheduling and control test operations and perform preliminary data processing, as well as to provide the interface with an external tester. Building these test operations on-chip allows for simplifying external tester interface and to reduce testing time. The testing procedure and the infrastructure required to test an A/D converter is described as an example.

Reducing the area overhead required by BIST structures can be achieved by reconfiguring existing hardware to perform test related control and processing functions. This work shows how the resources required for these operations can be implemented in-circuit, taking advantage of programmable logic available in the system. Structural and functional tests are performed using correlation to obtain i/sub DD/ and /spl nu//sub OUT/ cross-correlation signatures, and to measure gain, phase, and total harmonic distortion.

The development of a mixed-signal test bus infrastructure-IEEE P1149.4-is now in the final stages of the standardization process. Evaluating the test capabilities enabled by this infrastructure is an important step needed to support it as a well established standard. This paper presents experiments carried out with a test chip provided by the P1149.4 working group, which explore the architecture of the proposed analog boundary module to implement alternative testing methods. These include a method for parametric testing of passive components based on the monitoring of the power supply current, and a mixed current/voltage technique allowing the implementation of correlation for testing analog and mixed-signal macros.

The increasing complexity of mixed-signal boards makes an integrated analogue/digital testability approach an attractive proposition. This paper investigates one such approach based on the use of mixed-signal test support ICs together with standard board level test infrastructures. The architecture of a test support IC and preliminary experimental results are also presented.>

Discusses the need of a test infrastructure to support the testing of mixed-signal electronic systems, and discusses a general architecture for test support ICs that can be used to build it. An implementation of a subset of this architecture is described together with its application in a practical example.>