Present information technologies use semiconductor devices and magnetic/optical discs; however, they are all foreseen to face fundamental limitations within a decade. Therefore, superseding devices are required for the next paradigm of high-performance information technologies. "Single molecule devices" have been expected to be the most probable candidate; however, they have not been made practical since they were first proposed more than a quarter of a century ago. The major obstacles are the extreme difficulty in accessing a single molecule, and the very complicated electron states of a molecule connected to electrodes. With the advancements in scanning tunneling microscope (STM) and simulation technologies, the design and demonstration of single molecule devices are close to reality. This paper first reviews the architectures suitable for single molecule information processing, in which it is claimed that the performances of information processing is higher, if speed and element number product is larger in almost all architectures. Then, prospects for single molecule devices, including switching devices, wires, diodes, nanotubes, optical devices, storage devices and sensing devices for future information technologies and other advanced applications are described. Four milestones for realizing the peta/exa-floating operations per second (FLOPS) personal molecular supercomputer are proposed. Current status and necessary technologies of the first milestone are described and necessary technologies for the next three milestones are also discussed.

Technology challenges for silicon integrated circuits with a design rule of 0.1 /spl mu/m and below are addressed. We begin by reviewing the state-of-the-art CMOS technology at 0.25 /spl mu/m currently in development, covering a logic-oriented processes and dynamic random access memory (DRAM) processes. CMOS transistor structures are compared by introducing a figure of merit. We then examine scaling guidelines for 0.1 /spl mu/m which has started to deviate for optimized performance from the classical theory of constant-field scaling. This highlights the problem of nontrivial subthreshold current associated with the scaled-down CMOS with low threshold voltages. Interconnect issues are then considered to assess the performance of microprocessors in 0.1 /spl mu/m technology. 0.1 /spl mu/m technology will enable a microprocessor which runs at 1000 MHz with 500 million transistors. Challenges below 0.1 /spl mu/m are then addressed. New transistor and circuit possibilities such as silicon on insulator (SOI), dynamic-threshold (DT) MOSFET, and back-gate input MOS (BMOS) are discussed. Two problems below 0.1 /spl mu/m are highlighted. They are threshold voltage control and pattern printing. It is pointed out that the threshold voltage variations due to doping fluctuations is a limiting factor for scaling CMOS transistors for high performance. The problem with lithography below 0.1 /spl mu/m is the low throughput for a single probe. The use of massively parallel scanning probe assemblies working over the entire wafer is suggested to overcome the problem of low throughput.

A novel Josephson device with many desirable properties/spl minus/fast switching speed, high operation frequency, and low power dissipation/spl minus/has been researched these several years: the Quantum Flux Parametron (QFP). This paper discusses the interconnection problem of QFP circuits, where wire inductance matching and high clock rate restrict the lengths of interconnection wires. A layout model of QFP interconnection wires is clarified, and the effects of wire inductance matching on interconnection area and wire length are analyzed. The limitation comes from the bound of the number of squares of wires, therefore similar effects will exist where wire resistance is bounded. This paper discusses a simple wiring and buffering algorithm for QFP circuits, in which wire inductance is adjusted and the maximum wire length is controlled, to prove that any logic is realizable as a QFP circuit.>