Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page
Demo Data from VLDB 2026 / reviewers in the wild / expert

H. L. Tredennick

dblp:74/7032 · DBLP profile ↗
← Back
1ranked-venue papers
1as first author
0since 2021 · last 1977
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 77% Memory systems · 23%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
buffering		 0.011977
High-Speed Buffering for Variable Length Operands · ISCA 1977
Memory systems
cache		 0.011977
High-Speed Buffering for Variable Length Operands · ISCA 1977

Methods — techniques the papers use, named apart from their topics

buffering · 0.0
YearPublicationVenuePosition
1977 High-Speed Buffering for Variable Length Operands
H. L. Tredennick, Terry A. Welch
 ISCA1